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PRELIMINARY
Clock Generator for Intel® Calistoga Chipset
CY28447
Rev 1.0, November 20, 2006
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2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
Features
• Compliant to Intel® CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
• 96/100 MHz spreadable differential video clock
• 33 MHz PCI clocks
• Buffered Reference Clock 14.318MHz
• Low-voltage frequency select inputs
•I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
CPU
SRC
PCI
REF
DOT96
USB_48M
LCD
27M
x2 / x3
x9/11
x5
x 2
x 1
x 1
x1
x2
Pin Configuration
Block Diagram
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
VDD_SRC
154
VDD_SRC
SRCC_9
253
SRCC_2
SRCT_9
352
SRCT_2
VSS_SRC
451
SRCC_1
CPUC2_ITP / SRCC_10
550
SRCT_1
CPUT2_ITP / SRCT_10
649
VDD_SRC
VDDA
748
SRCC_0 / LCD100MC
VSSA
847
SRCT_0 / LCD100MT
IREF
946
CLKREQ1#
CPUC1
10
45
FSB/TEST_MODE
CPUT1
11
44
DOT96C / 27M_SS
VDD_CPU
12
43
DOT96T / 27M_NSS
CPUC0
13
42
VSS_48
CPUT0
14
41
48M / FSA
VSS_CPU
15
40
VDD_48
SCLK
16
39
VTT_PWRGD# / PD
SDATA
17
38
CLKREQ7#
VDD_REF
18
37
PCIF0/ITP_SEL
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
CY28447
IREF
VDD
REF[1:0]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
Divider
Divider
Divider
14.318MHz
Crystal
CPU
PLL
LVDS
PLL
Fixed
PLL
PLLReference
XIN
XOUT
PCI_STP#
FS[C:A]
VTT_PWRGD#/PD
CPUT[0:1]
CPUC[0:1]
SRCT(1:9])
VDD
PCI[1:4]
VDD
PCIF0
VDD_PCI
CPU_STP#
CLKREQ[1:9]#
VDD
FCTSEL1
SEL_CLKREQ
ITP_SEL
SRCC(1:9])
48M
VDD48
SRCT0/100MT_SST
SRCC0/100MC_SST
I2C
Logic
SDATA
SCLK
27MNon-spread
VDD48
Divider
27M
PLL
27MSpread
VDD48
VDD48
DOT96T
DOT96C