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KS8993M Datasheet(PDF) 44 Page - Micrel Semiconductor

Part No. KS8993M
Description  Integrated 3-Port 10/100 Managed Integrated 3-Port 10/100 Managed
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KS8993M Datasheet(HTML) 44 Page - Micrel Semiconductor

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Micrel, Inc.
KS8993M/ML/MI
April 2005
44
M9999-041205
MII Management (MIIM) Registers
The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I
2C, and SMI
interfaces can also be used to access these registers. The latter three interfaces use a different mapping
mechanism than the MIIM interface.
As defined in the IEEE 802.3 specification, the “PHYAD” are assigned as “0x1” for PHY port 1 and “0x2” for PHY
port 2. The “REGAD” supported are 0,1,2,3,4, and 5.
Register 0: MII Basic Control
Bit
Name
R/W
Description
Default
Reference
15
Soft reset
RO
NOT SUPPORTED
0
14
Loopback
R/W
=1, Loopback mode
=0, Normal operation
0
Reg. 29, bit 0
Reg. 45, bit 0
13
Force 100
R/W
=1, 100 Mbps
=0, 10 Mbps
0
Reg. 28, bit 6
Reg. 44, bit 6
12
AN enable
R/W
=1, Auto-negotiation enabled
=0, Auto-negotiation disabled
1
11
Power down
R/W
=1, Power down
=0, Normal operation
0
Reg. 29, bit 3
Reg. 45, bit 3
10
Isolate
RO
NOT SUPPORTED
0
9
Restart AN
R/W
=1, Restart auto-negotiation
=0, Normal operation
0
Reg. 29, bit 5
Reg. 45, bit 5
8
Force full
duplex
R/W
=1, Full duplex
=0, Half duplex
0
Reg. 28, bit 5
Reg. 44, bit 5
7
Collision test
RO
NOT SUPPORTED
0
6
Reserved
RO
0
5
Reserved
RO
0
4
Force MDI
R/W
=1, Force MDI (transmit on RXP / RXM pins)
=0, Normal operation (transmit on TXP / TXM
pins)
0
Reg. 29, bit 1
Reg. 45, bit 1
Register Number
Description
0x0
Basic Control Register
0x1
Basic Status Register
0x2
Physical Identifier I
0x3
Physical Identifier II
0x4
Auto-Negotiation Advertisement Register
0x5
Auto-Negotiation Link Partner Ability Register
0x6 – 0x1F
Not supported


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