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KS8993M Datasheet(PDF) 37 Page - Micrel Semiconductor

Part No. KS8993M
Description  Integrated 3-Port 10/100 Managed Integrated 3-Port 10/100 Managed
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KS8993M Datasheet(HTML) 37 Page - Micrel Semiconductor

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Micrel, Inc.
KS8993M/ML/MI
April 2005
37
M9999-041205
Port-Based Priority
With port based priority, each ingress port can be individually classified as a high priority receiving port. All
packets received at the high priority receiving port are marked as high priority, and will be sent to the high priority
transmit queue if the corresponding transmit queue is split. Bit 4 of registers 16, 32 and 48 is used to enable port
based priority for ports 1, 2 and 3, respectively. Optionally, the Px_PP strap-in pins can be used to enable this
feature.
802.1p-Based Priority
For 802.1p based priority, the KS8993M will examine the ingress (incoming) packets to determine whether they
are tagged. If tagged, the 3-bits priority field in the VLAN tag is retrieved and compared against the “priority base”
value, specified by register 2 bits [6:4]. The “priority base” value is programmable; its default value is 0x4.
The following figure illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Preamble
DA
TCI
86
6
2
length
LLC
Data
FCS
2
46-1500
4
1
Tagged Packet Type
(8100 for Ethernet)
802.1p
VLAN ID
Bytes
Bits
16
3
12
802.1q VLAN Tag
2
SA
VPID
Figure 6. 802.1p Priority Field Format
If an ingress packet has an equal or higher priority value than the "priority base" value, the packet will be placed in
the high priority transmit queue if the corresponding transmit queue is split. 802.1p based priority is enabled by bit
5 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the Px_1PEN strap-in pins can be used
to enable this feature.
The KS8993M provides the option to insert or remove the priority tagged frame's header at each individual egress
port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2 bytes Tag Control Information field
(TCI), is also refer to as the 802.1Q VLAN Tag.
Tag Insertion is enabled by bit 2 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the
Px_TAGINS strap-in pins can be used to enable this feature. At the egress port, untagged packets are tagged
with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52}
for ports 1, 2 and 3, respectively. The KS8993M will not add tags to already tagged packets.
Tag Removal is enabled by bit 1 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. Optionally, the
Px_TAGRM strap-in pins can be used to enable this feature. At the egress port, tagged packets will have their
802.1Q VLAN Tags removed. The KS8993M will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KS8993M to set the “User Priority Ceiling” at
any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field
of the ingress port, the packet’s priority field is replaced with the default tag’s priority field. The “User Priority
Ceiling” is enabled by bit 3 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
DiffServ-Based Priority
DiffServ-based priority uses registers 96 to 103. More details are provided at the beginning of the Advanced
Control Registers section.


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