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KS8993M Datasheet(PDF) 30 Page - Micrel Semiconductor

Part No. KS8993M
Description  Integrated 3-Port 10/100 Managed Integrated 3-Port 10/100 Managed
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KS8993M Datasheet(HTML) 30 Page - Micrel Semiconductor

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Micrel, Inc.
KS8993M/ML/MI
April 2005
30
M9999-041205
out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a
backpressure situation, the carrier sense type back pressure will be interrupted and those packets will be
transmitted instead. If there are no more packets to send, carrier sense type backpressure will be active again
until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier
sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent
reception of packets.
To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following:
1.
Aggressive back off (Global Register 3 (0x03), bit 0 or external strap-in pin SMAC = high)
2.
No excessive collision drop (Global Register 4 (0x04), bit 3 or external strap-in pin SMAC = high)
These bits are not set as defaults because this is not the IEEE standard.
Broadcast Storm Protection
The KS8993M has an intelligent option to protect the switch system from receiving too many broadcast packets.
Broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources
(bandwidth and available space in transmit queues). The KS8993M has the option to include “multicast packets”
for storm control. The broadcast storm rate parameters are programmed globally, and can be enabled or disabled
on a per port basis. The rate is based on a 67ms interval for 100BT and a 500ms interval for 10BT. At the
beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number
of bytes during the interval. The rate definition is described in Global Register 6 (0x06) and 7 (0x07). The default
setting for registers 6 and 7 is 0x63, which is 99 decimal. This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63
MII Interface Operation
The MII is specified by the IEEE 802.3 standards committee and provides a common interface between physical
layer and MAC layer devices. The MII Interface provided by the KS8993M is connected to the device’s third MAC.
The interface contains two distinct groups of signals: one for transmission and the other for reception. The
following table describes the signals used in the MII interface.
KS8993M PHY-Mode Connections
KS8993M MAC-Mode Connections
External MAC
Controller Signals
KS8993M
PHY Signals
Pin
Descriptions
External
PHY Signals
KS8993M
MAC Signals
MTXEN
SMTXEN
Transmit enable
MTXEN
SMRXDV
MTXER
SMTXER
Transmit error
MTXER
(not used)
MTXD3
SMTXD[3]
Transmit data bit 3
MTXD3
SMRXD[3]
MTXD2
SMTXD[2]
Transmit data bit 2
MTXD2
SMRXD[2]
MTXD1
SMTXD[1]
Transmit data bit 1
MTXD1
SMRXD[1]
MTXD0
SMTXD[0]
Transmit data bit 0
MTXD0
SMRXD[0]
MTXC
SMTXC
Transmit clock
MTXC
SMRXC
MCOL
SCOL
Collision detection
MCOL
SCOL
MCRS
SCRS
Carrier sense
MCRS
SCRS
MRXDV
SMRXDV
Receive data valid
MRXDV
SMTXEN
MRXER
(not used)
Receive error
MRXER
SMTXER
MRXD3
SMRXD[3]
Receive data bit 3
MRXD3
SMTXD[3]
MRXD2
SMRXD[2]
Receive data bit 2
MRXD2
SMTXD[2]
MRXD1
SMRXD[1]
Receive data bit 1
MRXD1
SMTXD[1]
MRXD0
SMRXD[0]
Receive data bit 0
MRXD0
SMTXD[0]
MRXC
SMRXC
Receive clock
MRXC
SMTXC
Table 3. MII Signals


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