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KS8993M Datasheet(PDF) 56 Page - Micrel Semiconductor

Part No. KS8993M
Description  Integrated 3-Port 10/100 Managed Integrated 3-Port 10/100 Managed
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KS8993M Datasheet(HTML) 56 Page - Micrel Semiconductor

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Micrel, Inc.
KS8993M/ML/MI
April 2005
56
M9999-041205
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
Bit
Name
R/W
Description
Default
7
Reserved
Reserved
0
6
Ingress VLAN
filtering
R/W
= 1, the switch will discard packets whose VID
port membership in VLAN table bits [18:16] does
not include the ingress port.
= 0, no ingress VLAN filtering.
0
5
Discard non
PVID packets
R/W
= 1, the switch will discard packets whose VID
does not match ingress port default VID.
= 0, no packets will be discarded
0
4
Force flow
control
R/W
= 1, will always enable flow control on the port,
regardless of AN result.
= 0, the flow control is enabled based on AN
result.
Pin value during
reset:
For port 1,
P1FFC pin
For port 2,
P2FFC pin
For port 3, this
bit has no
meaning. Flow
control is
controlled by
Reg. 6, bit 5.
3
Back pressure
enable
R/W
= 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure.
Pin value during
reset:
BPEN pin
2
Transmit
enable
R/W
= 1, enable packet transmission on the port
= 0, disable packet transmission on the port
1
1
Receive
enable
R/W
= 1, enable packet reception on the port
= 0, disable packet reception on the port
1
0
Learning
disable
R/W
= 1, disable switch address learning capability
= 0, enable switch address learning
0
Note: Bits [2:0] are used for spanning tree support (see page 33).
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Bit
Name
R/W
Description
Default
7-0
Default tag
[15:8]
R/W
Port’s default tag, containing
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
0x00


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