Philips Semiconductors

Product specification

PowerMOS transistor

PHW7N60

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

field-effect power transistor in a

plastic

envelope

featuring

high

V

DS

Drain-source voltage

600

V

avalanche energy capability, stable

I

D

Drain current (DC)

7

A

off-state

characteristics,

fast

P

tot

Total power dissipation

147

W

switching and high thermal cycling

R

DS(ON)

Drain-source on-state resistance

1.2

Ω

performance

with

low

thermal

resistance. Intended

for use in

Switched Mode Power Supplies

(SMPS), motor control circuits and

general

purpose

switching

applications.

PINNING - SOT429 (TO247)

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I

D

Continuous drain current

T

25 ˚C; V

-

7

A

T

-

4.5

A

I

DM

Pulsed drain current

T

-

28

A

P

D

Total dissipation

T

-

147

W

∆P

Linear derating factor

T

-

1.176

W/K

V

GS

Gate-source voltage

-

± 30

V

E

AS

Single pulse avalanche

V

-

570

mJ

energy

V

I

AS

Peak avalanche current

V

7

A

V

T

Operating junction and

- 55

150

˚C

storage temperature range

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

-

0.85

K/W

mounting base

R

th j-a

Thermal resistance junction to

-

45

-

K/W

ambient

2

3

1

d

g

s

June 1997

1

Rev 1.000