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PHT11N06LT Datasheet(PDF) 4 Page - NXP Semiconductors |
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PHT11N06LT Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 9 page Philips Semiconductors Product specification TrenchMOS ™ transistor PHT11N06LT Logic level FET Fig.1. Normalised power dissipation. PD% = 100 ⋅P D/PD 25 ˚C = f(Tsp) Fig.2. Normalised continuous drain current. ID% = 100 ⋅I D/ID 25 ˚C = f(Tsp); conditions: VGS ≥ 5 V Fig.3. Safe operating area. T sp = 25 ˚C I D & IDM = f(VDS); IDM single pulse; parameter tp Fig.4. Transient thermal impedance. Z th j-sp = f(t); parameter D = tp/T Fig.5. Typical output characteristics, T j = 25 ˚C. I D = f(VDS); parameter VGS Fig.6. Typical on-state resistance, T j = 25 ˚C. R DS(ON) = f(ID); parameter VGS 0 20 40 60 80 100 120 140 Tmb / C PD% Normalised Power Derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1E-07 1E-05 1E-03 1E-01 1E+01 t / s Zth / (K/W) 1E+02 3E+01 1E+01 3E+00 1E+00 3E-01 1E-01 3E-02 1E-02 0 0.5 0.2 0.1 0.05 0.02 D = tp tp T T P t D BUK9840-55 0 20 40 60 80 100 120 140 Tmb / C ID% Normalised Current Derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0246 8 10 0 5 10 15 20 2.2 2.4 2.6 2.8 3.0 3.2 3.4 4 3.6 10 5 ID/A VGS/V = BUKX840-55 VDS/V ID/A 1 us 10 us 100 us 1 ms 10 ms 100 ms tp = 0.1 1 10 100 0.1 1 10 55 RDS(ON) = VDS/ID DC 0 5 10 15 20 25 20 30 40 50 60 70 80 RDS(ON)/mOhm VGS/V = ID/A 5 4 3.6 3.4 3.2 3 January 1998 4 Rev 1.100 |
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