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STM802TDS6F Datasheet(PDF) 6 Page - STMicroelectronics

Part # STM802TDS6F
Description  3V Supervisor with Battery Switchover
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM802TDS6F Datasheet(HTML) 6 Page - STMicroelectronics

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Pin Descriptions
MR (Manual Reset). A logic low on /MR asserts
the reset output. Reset remains asserted as long
as MR is low and for trec after MR returns high.
This active-low input has an internal pull-up. It can
be driven from a TTL or CMOS logic line, or short-
ed to ground with a switch. Leave open if unused.
WDI (Watchdog Input). If WDI remains high or
low for 1.6sec, the internal watchdog timer runs
out and reset is triggered. The internal watchdog
timer clears while reset is asserted or when WDI
sees a rising or falling edge.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
RST (Active-low Reset). Pulses
low
for
trec
when triggered, and stays low whenever VCC is
below the reset threshold or when MR is a logic
low. It remains low for trec after either VCC rises
above the reset threshold, the watchdog triggers a
reset, or MR goes from low to high.
RST (Active-high Reset - Open Drain). Pulses
high for trec when triggered, and stays high when-
ever VCC is above the reset threshold or when MR
is a logic high. It remains high for trec after either
VCC falls below the reset threshold, the watchdog
triggers a reset, or MR goes from high to low.
PFI (Power-fail Input). When PFI is less than
VPFI or when VCC falls below VSW (2.4V), PFO
goes low; otherwise, PFO remains high. Connect
to ground if unused.
PFO (Power-fail Output). When PFI is less than
VPFI, or VCC falls below VSW, PFO goes low; oth-
erwise, PFO remains high. Leave open if unused.
VOUT (Supply Output Voltage). When VCC is
above the switchover voltage (VSO), VOUT is con-
nected to VCC through a P-channel MOSFET
switch. When VCC falls below VSO, VBAT connects
to VOUT. Connect to VCC if no battery is used.
Vccsw (VCC Switch Output). When
VOUT
switches to battery, Vccsw is high. When VOUT
switches back to VCC, Vccsw is low. It can be used
to drive gate of external PMOS transistor for IOUT
requirements exceeding 75mA.
E (Chip Enable Input). The input to the chip-en-
able gating circuit. Connect to ground if unused.
ECON (Conditional Chip Enable). ECON
goes
low only when E is low and reset is not asserted. If
ECON is low when reset is asserted, ECON will re-
main low for 15µs or until E goes high, whichever
occurs first. In the disabled mode, ECON is pulled
up to VOUT.
VBAT (Back-up Battery Input). When VCC falls
below VSO, VOUT switches from VCC to VBAT.
When VCC rises above VSO + hysteresis, VOUT re-
connects to VCC. VBAT may exceed VCC. Connect
to VCC if no battery is used.
Table 3. Pin Description
Pin
Name
Function
STM795
STM690
STM802
STM704
STM806
STM804
STM805
––6–
MR
Push-button Reset Input
–6–6
WDI
Watchdog Input
777–
RST
Active-Low Reset Output
–––7
RST
Active-High Reset Output
–444
PFI
Power-fail Input
–555
PFO
Power-fail Output
1111
VOUT
Supply Output for External LPSRAM
2222
VCC
Supply Voltage
3–––
Vccsw
VCC Switch Output
4333
VSS
Ground
5–––
E
Chip Enable Input
6–––
ECON
Conditioned Chip Enable Output
8888
VBAT
Backup-Battery Input


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