LHF32FB7

2

LH28F320BFB-PBTL60

32Mbit (2Mbit

×16)

Page Mode Dual Work Flash MEMORY

32M density with 16Bit I/O Interface

High Performance Reads

• 60/25ns 8-Word Page Mode

Configurative 4-Plane Dual Work

• Flexible Partitioning

• Read operations during Block Erase or (Page Buffer)

Program

• Status Register for Each Partition

Low Power Operation

• 2.7V Read and Write Operations

in Static Mode

Enhanced Code + Data Storage

• 5

µs Typical Erase/Program Suspends

OTP (One Time Program) Block

• 4-Word Factory-Programmed Area

• 4-Word User-Programmable Area

High Performance Program with Page Buffer

• 16-Word Page Buffer

• 5

µs/Word (Typ.) at 12V V

PP

Operating Temperature 0

°C to +70°C

CMOS Process (P-type silicon substrate)

Flexible Blocking Architecture

• Eight 4K-word Parameter Blocks

• Sixty-three 32K-word Main Blocks

• Bottom Parameter Location

Enhanced Data Protection Features

• Individual Block Lock and Block Lock-Down with

Zero-Latency

• All blocks are locked at power-up or device reset.

• Block Erase, Full Chip Erase, (Page Buffer) Word

Program Lockout during Power Transitions

Automated Erase/Program Algorithms

• 3.0V Low-Power

11µs/Word (Typ.)

Programming

• 12V No Glue Logic 9

µs/Word (Typ.)

Production Programming and 0.5s Erase (Typ.)

Cross-Compatible Command Support

• Basic Command Set

• Common Flash Interface (CFI)

Extended Cycling Capability

• Minimum 100,000 Block Erase Cycles

0.8mm pitch 48-Ball CSP

Not designed or rated as radiation hardened

The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low

power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can

battery life for portable applications.

The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus

eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual

work operation.

The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main

Blocks that provide maximum flexibility for safe nonvolatile code and data storage.

Fast program capability is provided through the use of high speed Page Buffer Program.

Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.

* ETOX is a trademark of Intel Corporation.

Rev. 2.44