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SN65HVD234DR Datasheet(PDF) 5 Page - Texas Instruments |
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SN65HVD234DR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 27 page  SN65HVD233 SN65HVD234 SN65HVD235 SLLS557D − NOVEMBER 2002 REVISED JUNE 2005 www.ti.com 5 DRIVER SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT RS at 0 V, See Figure 4 35 85 tPLH Propagation delay time, low-to-high-level output RS with 10 kΩ to ground, See Figure 4 70 125 ns tPLH Propagation delay time, low-to-high-level output RS with 100 kΩ to ground, See Figure 4 500 870 ns RS at 0 V, See Figure 4 70 120 tPHL Propagation delay time, high-to-low-level output RS with 10 kΩ to ground, See Figure 4 130 180 ns tPHL Propagation delay time, high-to-low-level output RS with 100 kΩ to ground, See Figure 4 870 1200 ns RS at 0 V, See Figure 4 35 tsk(p) Pulse skew (|tPHL – tPLH|) RS with 10 kΩ to ground, See Figure 4 60 ns tsk(p) Pulse skew (|tPHL – tPLH|) RS with 100 kΩ to ground, See Figure 4 370 ns tr Differential output signal rise time RS at 0 V, See Figure 4 20 70 ns tf Differential output signal fall time RS at 0 V, See Figure 4 20 70 ns tr Differential output signal rise time RS with 10 kΩ to ground, See Figure 4 30 135 ns tf Differential output signal fall time RS with 10 kΩ to ground, See Figure 4 30 135 ns tr Differential output signal rise time RS with 100 kΩ to ground, See Figure 4 350 1400 ns tf Differential output signal fall time RS with 100 kΩ to ground, See Figure 4 350 1400 ns ten(s) Enable time from standby to dominant See Figures 8 and 9 0.6 1.5 s ten(z) Enable time from sleep to dominant See Figures 8 and 9 1 5 µs (1) All typical values are at 25°C and with a 3.3 V supply. RECEIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going input threshold voltage 750 900 VIT− Negative-going input threshold voltage AB at 0 V, LBK at 0 V, EN at VCC, See Table 1 500 650 mV Vhys Hysteresis voltage (VIT+ − VIT−) AB at 0 V, LBK at 0 V, EN at VCC, See Table 1 100 mV VOH High-level output voltage IO = −4 mA, See Figure 6 2.4 V VOL Low-level output voltage IO = 4 mA, See Figure 6 0.4 V CANH or CANL at 12 V 150 500 II Bus input current CANH or CANL at 12 V, VCC at 0 V Other bus pin at 0 V, D at 3 V, AB at 0 V, 200 600 A II Bus input current CANH or CANL at −7 V D at 3 V, AB at 0 V, LBK at 0 V, RS at 0 V, EN at VCC −610 −150 µA CANH or CANL at −7 V, VCC at 0 V LBK at 0 V, RS at 0 V, EN at VCC −450 −130 CI Input capacitance (CANH or CANL) Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5V, D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC 40 pF CID Differential input capacitance Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5V, D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC 20 pF RID Differential input resistance D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC 40 100 k Ω RIN Input resistance (CANH or CANL) D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC 20 50 k Ω Sleep EN at 0 V, D at VCC, Rs at 0 V or VCC 0.05 2 Standby RS at VCC, D at VCC, AB at 0 V, LBK at 0 V, EN at VCC 200 600 µA ICC Supply current Dominant D at 0 V, No Load, RS at 0 V, LBK at 0 V, AB at 0 V, EN at VCC 6 mA Recessive D at VCC, No Load, RS at 0 V, LBK at 0 V, AB at 0 V, EN at VCC 6 mA (1) All typical values are at 25°C and with a 3.3 V supply. |
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