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DSP56857BUE Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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DSP56857BUE Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 53 page  56857 Technical Data, Rev. 6 4 Freescale Semiconductor Part 1 Overview 1.1 56857 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Four (4) 36-bit accumulators including extension bits • 16-bit bidirectional shifter • Parallel instruction set with unique DSP addressing modes • Hardware DO and REP loops • Three (3) internal address buses • Four (4) internal data buses • Instruction set supports both DSP and controller functions • Four (4) hardware interrupt levels • Five (5) software interrupt levels • Controller-style addressing modes and instructions for compact code • Efficient C Compiler and local variable support • Software subroutine and interrupt stack with depth limited only by memory • JTAG/Enhanced OnCE debug programming interface 1.1.2 Memory • Harvard architecture permits up to three (3) simultaneous accesses to program and data memory •On-Chip Memory —40K × 16-bit Program RAM —24K × 16-bit Data RAM —1K × 16-bit Boot ROM — Chip Select Logic used as dedicated GPIO 1.1.3 Peripheral Circuits for 56857 • General Purpose 16-bit Quad Timer* •Two Serial Communication Interfaces (SCI)* • Serial Peripheral Interface (SPI) Port* • Two (2) Enhanced Synchronous Serial Interface (ESSI) modules* • Computer Operating Properly (COP)/Watchdog Timer • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging • Six (6) independent channels of DMA |
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