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56800ERM Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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56800ERM Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 52 page  56855 Technical Data, Rev. 6 8 Freescale Semiconductor Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56855 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals present. 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed. Table 2-1 56855 Functional Group Pin Allocations Functional Group Number of Pins Power (VDD, VDDIO, or VDDA) (4, 10, 1)1 Ground (VSS, VSSIO,or VSSA) (4, 10, 1)1 PLL and Clock 3 External Bus Signals 39 External Chip Select* 4 Interrupt and Program Control 72 Enhanced Synchronous Serial Interface (ESSI0) Port* 6 Serial Communications Interface (SCI0) Ports* 2 Serial Communications Interface (SCI1) Ports* 2 Quad Timer Module Port* 1 JTAG/Enhanced On-Chip Emulation (EOnCE) 6 *Alternately, GPIO pins |
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