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56852 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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56852 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 48 page  56852 Technical Data, Rev. 8 Freescale Semiconductor 3 56852 Block Diagram JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit PLL Clock Generator 16-Bit 56800E Core XTAL EXTAL Interrupt Controller COP/ Watch- dog 1 Quad Timer or A17, A18 2 CLKO muxed (A20) External Bus Interface Unit 6 RESET IRQA IRQB VDD VSSIO VDDA VSSA WR Enable RD Enable CS[2:0] muxed (GPIOA) A0-16 MODE D0-D12[12:0] 6 Program Memory 6144 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 4096 x 16 SRAM PDB PDB XAB1 XAB2 XDB2 CDBR SSI or SPI or GPIOC SCI or GPIOE IPBus Bridge (IPBB) 3 muxed (D13-15) 3 6 A17-18 muxed (timer pins) A19 muxed (CS3) D13-15 muxed (Mode A,B,C) VDDIO 6 Integration Module System P O R O S C Decoding Peripherals Peripheral Address Decoder Peripheral Device Selects System Address Decoder RW Control IPAB IPWDB IPRDB 2 System Device System Bus Control R/W Control Memory PAB PAB CDBW CDBR CDBW Clock resets VSS 3 SSI or SPI or GPIOC External Data Bus Switch Bus Control External Address Bus Switch DSP56852 General Description • 120 MIPS at 120MHz • 6K x 16-bit Program SRAM • 4K x 16-bit Data SRAM • 1K x 16-bit Boot ROM • 21 External Memory Address lines, 16 data lines and four chip selects • One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) • One (1) Serial Communication Interface (SCI) • Interrupt Controller • General Purpose 16-bit Quad Timer • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Computer Operating Properly (COP)/Watchdog Timer • 81-pin MAPBGA package •Up to 11 GPIO |
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