AD9869 datasheet(8/36 Pages) AD

Part #	AD9869

Description	Broadband Modem Mixed-Signal Front End

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AD9869

Rev. 0 | Page 8 of 36

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter

Temp

Test Level1

Min

Typ

Max

Unit

READ OPERATION2 (See Figure 9)

Output Data Rate

Full

II

20

80

MSPS

Three-State Output Enable Time (tPZL)

Full

II

3

ns

Three-State Output Disable Time (tPLZ)

Full

II

3

ns

Rx Data Valid Time (tVT)

Full

II

1.5

ns

Rx Data Output Delay (tOD)

Full

II

4

ns

WRITE OPERATION (See Figure 8)

Input Data Rate (2× Interpolation)

Full

II

40

80

MSPS

Input Data Rate (4× Interpolation)

Full

II

20

50

MSPS

Tx Data Setup Time (tDS)

Full

II

1

ns

Tx Data Hold Time (tDH)

Full

II

2.5

ns

Latch Enable Time (tEN)

Full

II

3

ns

Latch Disable Time (tDIS)

Full

II

3

ns

1 See the Explanation of Test Levels section.

2 CLOAD = 5 pF for digital data outputs.

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter

Temp

Test Level1

Min

Typ

Max

Unit

Tx PATH INTERFACE (See Figure 12)

Input Nibble Rate (2× Interpolation)

Full

II

80

160

MSPS

Input Nibble Rate (4× Interpolation)

Full

II

40

100

MSPS

Tx Data Setup Time (tDS)

Full

II

2.5

ns

Tx Data Hold Time (tDH)

Full

II

1.5

ns

Rx PATH INTERFACE2 (See Figure 13)

Output Nibble Rate

Full

II

40

160

MSPS

Rx Data Valid Time (tDV)

Full

II

3

ns

Rx Data Hold Time (tDH)

Full

II

0

ns

1 See the Explanation of Test Levels section.

2 CLOAD = 5 pF for digital data outputs.

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