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AD7367BRUZ-500RL7 Datasheet(PDF) 25 Page - Analog Devices |
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AD7367BRUZ-500RL7 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 28 page  AD7366/AD7367 Rev. 0 | Page 25 of 28 Table 13. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) Setting Description RCKFE = 1 Sample data with falling edge of RSCLK LRFS = 1 Active low frame signal RFSR = 1 Frame every word IRFS = 1 Internal RFS used RLSBIT = 0 Receive MSB first RDTYPE = 00 Zero fill IRCLK = 1 Internal receive clock RSPEN = 1 Receive enabled SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) TFSR = RFSR = 1 Table 14. The SPORT0 Receive Configuration 2 Register (SPORT0_RCR2) Setting Description RXSE = 1 Secondary side enabled SLEN = 1111 16-bit data-word (or can be set to 1101 for 14-bit data-word) AD7366/AD7367 TO TMS320VC5506 The serial interface on the TMS320VC5506 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7366/AD7367. The CS input allows easy interfacing between the TMS320VC5506 and the AD7366/AD7367 without any glue logic required. The serial ports of the TMS320VC5506 are set up to operate in burst mode with internal CLKX0 (TX serial clock on Serial Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial port control registers (SPC) must be setup as shown in Table 15. Table 15. Serial Port Control Register Set Up SPC FO FSM MCM TXM SPC0 0 1 1 1 SPC1 0 1 0 0 The connection diagram is shown in Figure 31. The VDRIVE pin of the AD7366/AD7367 takes the same supply voltage as that of the TMS320VC5506. This allows the ADC to operate at a higher voltage than its serial interface and, therefore, the TMS320VC5506, if necessary. FSR1 FSR0 AD7366/ AD7367* SCLK TMS320VC5506* *ADDITIONAL PINS OMITTED FOR CLARITY. CLKX0 DR1 CLKR1 CLKX1 DOUTB DOUTA VDRIVE VDD CS FSX0 DR0 CLKR0 INTn XF CNVST BUSY Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506 As with the previous interfaces, conversion can be initiated from the TMS320VC5506 or from an external source, and the processor is interrupted when the conversion sequence is completed. AD7366/AD7367 TO DSP563xx The connection diagram in Figure 32 shows how the AD7366/ AD7367 can be connected to the enhanced synchronous serial interface (ESSI) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each is operated in synchro- nous mode (Bit SYN = 1 in the CRB register) with internally generated word length frame sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Normal operation of the ESSI is selected by making MOD = 0 in the CRB register. Set the word length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB register should be set to 1 so that the frame sync is negative. |
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