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AD8153ACPZ Datasheet(PDF) 13 Page - Analog Devices |
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AD8153ACPZ Datasheet(HTML) 13 Page - Analog Devices |
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13 / 24 page  AD8153 Rev. 0 | Page 13 of 24 THEORY OF OPERATION The AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer. There are three operating modes: pin mode, serial mode, and mixed mode. In pin mode, lane switching, equalization, and pre-emphasis are controlled using external pins. In serial mode, an I2C interface is used to control the device and to provide access to advanced features, such as additional pre-emphasis settings and output disable. In mixed mode, the user accesses the advanced features using I2C but controls lane switching using external pins. SWITCH CONFIGURATIONS On the demultiplexer side, the AD8153 relays received data on Input Port C to Output Port A and/or Output Port B, depending on the state of the BICAST and SEL bits. On the multiplexer side, the device relays received data on either Input Port A or Input Port B to Output Port C, depending on the state of the SEL bit. When bicast mode is off, the outputs of either Port A or Port B are in an idle state. In the idle state, the output tail current is set to 0, and the P and N sides of the lane are pulled up to the output termination voltage through the on-chip termination resistors. The device also supports loopback on all ports, illustrated in Figure 31. Enabling loopback on any port overrides configurations set by the BICAST and SEL control bits. Table 5 summarizes the possible switch configurations. The AD8153 output disable feature can be used to force an output into the idle (powered-down) state. This feature is only accessible through the serial control interface. 1:2 DEMUX 2:1 MUX INPUT C OUTPUT C PORT C LOOPLOCK OUTPUT A OUTPUT B INPUT A INPUT B PORT A LOOPBACK PORT B LOOPBACK Figure 31. Loopback Configurations Table 5. Switch Configurations LB_A LB_B LB_C SEL BICAST Output A Output B Output C 0 0 0 0 0 Input C Idle Input A 0 0 0 0 1 Input C Input C Input A 0 0 0 1 0 Idle Input C Input B 0 0 0 1 1 Input C Input C Input B 0 0 1 0 0 Input C Idle Input C 0 0 1 X 1 Input C Input C Input C 0 0 1 1 0 Idle Input C Input C 0 1 0 0 X Input C Input B Input A 0 1 0 1 0 Idle Input B Input B 0 1 0 1 1 Input C Input B Input B 0 1 1 0 X Input C Input B Input C 0 1 1 1 0 Idle Input B Input C 0 1 1 X 1 Input C Input B Input C 1 0 0 0 0 Input A Idle Input A 1 0 0 0 1 Input A Input C Input A 1 0 0 1 X Input A Input C Input B 1 0 1 0 0 Input A Idle Input C |
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