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MC9S12C128MPB Datasheet(PDF) 54 Page - Freescale Semiconductor, Inc |
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MC9S12C128MPB Datasheet(HTML) 54 Page - Freescale Semiconductor, Inc |
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54 / 680 page  Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128) 54 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.23 1.3.4.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. This pin is not available in the 48- / 52-pin package versions. 1.3.4.14 PE1 / IRQ — Port E Input Pin [1] / Maskable Interrupt Pin The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. 1.3.4.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin The XIRQ input provides a means of requesting a non-maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register. 1.3.4.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] PAD7–PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In order to use a PAD pin as a standard input, the corresponding ATDDIEN register bit must be set. These bits are cleared out of reset to configure the PAD pins for A/D operation. When the A/D converter is active in multi-channel mode, port inputs are scanned and converted irrespective of Port AD configuration. Thus Port AD pins that are configured as digital inputs or digital outputs are also converted in the A/D conversion sequence. 1.3.4.17 PP[7] / KWP[7] — Port P I/O Pin [7] PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. 1.3.4.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit stop or wait mode. This pin is not available in the 48- / 52-pin package versions. During MCU expanded modes of operation, this pin is used to enable |
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