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MC9S12C128VPB Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc |
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MC9S12C128VPB Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc |
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98 / 680 page  Chapter 2 Port Integration Module (PIM9C32) Block Description 98 MC9S12C-Family / MC9S12GC-Family Freescale Semiconductor Rev 01.23 2.3.2.5.3 Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. 2.3.2.5.4 Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. Module Base + 0x002A 76543210 R DDRJ7 DDRJ6 000000 W Reset 0 0 —————— = Unimplemented or Reserved Figure 2-34. Port J Data Direction Register (DDRJ) Table 2-28. DDRJ Field Descriptions Field Description 7–6 DDRJ[7:6] Data Direction Port J — This register configures port pins J[7:6] as either input or output. DDRJ[7:6] — Data Direction Port J 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register. Module Base + 0x002B 76543210 R RDRJ7 RDRJ6 000000 W Reset 0 0 —————— = Unimplemented or Reserved Figure 2-35. Port J Reduced Drive Register (RDRJ) Table 2-29. RDRJ Field Descriptions Field Description 7–6 RDRJ[7:6] Reduced Drive Port J — This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. |
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