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74LVCH244ABQ Datasheet(PDF) 2 Page - NXP Semiconductors |
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74LVCH244ABQ Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 17 page 2003 Oct 30 2 Philips Semiconductors Product specification Octal buffer/line driver with 5 V tolerant inputs/outputs (3-state) 74LVC244A; 74LVCH244A FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • High-impedance when VCC =0V • Bushold on all data inputs (74LVCH244A only) • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74LVC244A/74LVCH244A is a high performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC244A/74LVCH244A is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. The 244 is functionally identical to the 240, but the 240 has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay 1An to 1Yn, 2An to 2Yn CL = 50 pF; VCC = 3.3 V 2.8 ns CI input capacitance 4.0 pF CPD power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 10 pF |
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