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DP83816 Datasheet(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. DP83816
Description  10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II )
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83816 Datasheet(HTML) 2 Page - National Semiconductor (TI)

  DP83816 Datasheet HTML 1Page - National Semiconductor (TI) DP83816 Datasheet HTML 2Page - National Semiconductor (TI) DP83816 Datasheet HTML 3Page - National Semiconductor (TI) DP83816 Datasheet HTML 4Page - National Semiconductor (TI) DP83816 Datasheet HTML 5Page - National Semiconductor (TI) DP83816 Datasheet HTML 6Page - National Semiconductor (TI) DP83816 Datasheet HTML 7Page - National Semiconductor (TI) DP83816 Datasheet HTML 8Page - National Semiconductor (TI) DP83816 Datasheet HTML 9Page - National Semiconductor (TI) Next Button
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Table of Contents
1.0
Connection Diagram . . . . . . . . . . . . . . . . . . 4
1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4
2.0
Pin Description . . . . . . . . . . . . . . . . . . . . . . 5
3.0
Functional Description . . . . . . . . . . . . . . . 11
3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.2 Tx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3 Rx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Buffer Management . . . . . . . . . . . . . . . . . 13
3.2.1 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.4 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Interface Definitions . . . . . . . . . . . . . . . . . 14
3.3.1 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.2 Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Auto-Negotiation Register Control . . . . . . . . . . . . . 16
3.4.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . 16
3.4.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . 17
3.4.5 Enabling Auto-Negotiation via Software . . . . . . . . 17
3.4.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . 17
3.5 LED Interfaces . . . . . . . . . . . . . . . . . . . . . 17
3.6 Half Duplex vs. Full Duplex . . . . . . . . . . . 18
3.7 Phy Loopback . . . . . . . . . . . . . . . . . . . . . 18
3.8 Status Information . . . . . . . . . . . . . . . . . . 18
3.9 100BASE-TX TRANSMITTER . . . . . . . . . 18
3.9.1 Code-group Encoding and Injection . . . . . . . . . . . 19
3.9.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . 20
3.9.4 Binary to MLT-3 Convertor / Common Driver . . . . 20
3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 21
3.10.1 Input and Base Line Wander Compensation . . . . 21
3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . . 23
3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . 24
3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . . 25
3.10.7 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.8 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . . 25
3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . . 25
3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 25
3.11 10BASE-T Transceiver Module . . . . . . . . 26
3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.3 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.4 Normal Link Pulse Detection/Generation . . . . . . . 26
3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.6 Automatic Link Polarity Detection . . . . . . . . . . . . . 27
3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . . 27
3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . 27
3.11.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 27
3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 27
3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . . 27
3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 27
3.12.3 MII Serial Management Access . . . . . . . . . . . . . 28
3.12.4 Serial Management Access Protocol . . . . . . . . . 28
3.12.5 Nibble-wide MII Data Interface . . . . . . . . . . . . . . 28
3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 29
3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.0
Register Set . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 Configuration Registers . . . . . . . . . . . . . . 30
4.1.1 Configuration Identification Register . . . . . . . . . . . 30
4.1.2 Configuration Command and Status Register . . . 31
4.1.3 Configuration Revision ID Register . . . . . . . . . . . 32
4.1.4 Configuration Latency Timer Register . . . . . . . . . 33
4.1.5 Configuration I/O Base Address Register . . . . . . . 33
4.1.6 Configuration Memory Address Register . . . . . . . 34
4.1.7 Configuration Subsystem Identification Register . 34
4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 35
4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 35
4.1.10 Configuration Interrupt Select Register . . . . . . . . 36
4.1.11 Power Management Capabilities Register . . . . . 36
4.1.12 Power Management Control and Status Register 37
4.2 Operational Registers . . . . . . . . . . . . . . . 38
4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.2 Configuration and Media Status Register . . . . . . . 40
4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 42
4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 43
4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 44
4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 45
4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 47
4.2.9 Interrupt Holdoff Register . . . . . . . . . . . . . . . . . . . 47
4.2.10 Transmit Descriptor Pointer Register . . . . . . . . . 48
4.2.11 Transmit Configuration Register . . . . . . . . . . . . . 48
4.2.12 Receive Descriptor Pointer Register . . . . . . . . . . 50
4.2.13 Receive Configuration Register . . . . . . . . . . . . . 51
4.2.14 CLKRUN Control/Status Register . . . . . . . . . . . . 52
4.2.15 Wake Command/Status Register . . . . . . . . . . . . 54
4.2.16 Pause Control/Status Register . . . . . . . . . . . . . . 56
4.2.17 Receive Filter/Match Control Register . . . . . . . . 57
4.2.18 Receive Filter/Match Data Register . . . . . . . . . . 58
4.2.19 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 59
4.2.20 Boot ROM Address Register . . . . . . . . . . . . . . . . 63
4.2.21 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 63
4.2.22 Silicon Revision Register . . . . . . . . . . . . . . . . . . 63
4.2.23 Management Information Base Control Register 64
4.2.24 Management Information Base Registers . . . . . . 65
4.3 Internal PHY Registers . . . . . . . . . . . . . . . 66
4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 66
4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 67
4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 68
4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 68
4.3.5 Auto-Negotiation Advertisement Register . . . . . . 68
4.3.6 Auto-Negotiation Link Partner Ability Register . . . 69
4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 70
4.3.8 Auto-Negotiation Next Page Transmit Register . . 70
4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 71
4.3.10 MII Interrupt Control Register . . . . . . . . . . . . . . . 73
4.3.11 MII Interrupt Status and Misc. Control Register . 73
4.3.12 False Carrier Sense Counter Register . . . . . . . . 74
4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 74
4.3.14 100 Mb/s PCS Configuration and Status Register 74
4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 75
4.3.16 10BASE-T Status/Control Register . . . . . . . . . . . 76
5.0
Buffer Management . . . . . . . . . . . . . . . . . . 77
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . 79


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