Si5326

8

Confidential Rev. 0.2

4C2B

O

LVCMOS

CKIN2 Invalid Indicator.

This pin functions as a LOS (and optionally FOS) alarm indicator

for CKIN2 if CK2_BAD_PIN =1.

0 = CKIN2 present.

1 = LOS (FOS) on CKIN2.

The active polarity can be changed by CK_BAD_POL. If

CK2_BAD_PIN = 0, the pin tristates.

5, 10, 32

Supply

Supply.

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass

capacitors should be associated with the following Vdd pins:

50.1 µF

10

0.1 µF

32

0.1 µF

A 1.0 µF should be placed as close to the device as is practical.

7

6

XB

XA

IAnalog

External Crystal or Reference Clock.

External crystal should be connected to these pins to use internal

oscillator based reference. If external reference is used, apply ref-

erence clock to XA input and leave XB pin floating. External refer-

ence must be from a high-quality clock source (TCXO, OCXO).

Frequency of crystal or external clock is set by RATE[1:0] pins.

8, 31

GND

GND

Supply

Ground.

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device.

11

15

RATE0

RATE1

I

3-Level

External Crystal or Reference Clock Rate.

Three level inputs that select the type and rate of external crystal

or reference clock to be applied to the XA/XB port.

LM = 38.88 MHz external clocks

MM = 114.285 MHz 3rd OT crystal

HH = converts part to Si5325, and no external crystal or reference

is needed

16

17

CKIN1+

CKIN1–

IMulti

Clock Input 1.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

12

13

CKIN2+

CKIN2–

IMulti

Clock Input 2.

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

18

LOL

O

LVCMOS

PLL Loss of Lock Indicator.

This pin functions as the active high PLL loss of lock indicator if the

LOL_PIN register bit is set to 1.

0 = PLL locked.

1 = PLL unlocked.

If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by

the LOL_POL bit. The PLL lock status will always be reflected in

the LOL_INT read only register bit.

Pin #

Pin Name

I/O

Signal Level

Description

Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map.