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PCK2023 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. PCK2023
Description  CK408 66/100/133/200 MHz spread spectrum differential system clock generator
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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PCK2023 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product data
PCK2023
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
2001 Sep 07
5
FREQUENCY SELECT/FUNCTION TABLE
S2
S1
S0
CPU
3V66
66BUFF/
3V66
66In/
3V66_5
PCIF/PCI
REF 0
USB/DOT
3V66_1/
VCH
1
0
0
66 MHz
66 MHz
66 In
66 input
66 In/2
14.318 MHz
48 MHz
66/48 MHz
1
0
1
100 MHz
66 MHz
66 In
66 input
66 In/2
14.318 MHz
48 MHz
66/48 MHz
1
1
0
200 MHz
66 MHz
66 In
66 input
66 In/2
14.318 MHz
48 MHz
66/48 MHz
1
1
1
133 MHz
66 MHz
66 In
66 input
66 In/2
14.318 MHz
48 MHz
66/48 MHz
0
0
0
66 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
66/48 MHz
0
0
1
100 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
66/48 MHz
0
1
0
200 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
66/48 MHz
0
1
1
133 MHz
66 MHz
66 MHz
66 MHz
33 MHz
14.318 MHz
48 MHz
66/48 MHz
Mid
0
0
Low
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi-Z
Mid
0
1
Tclk/2
Tclk/4
Tclk/4
Tclk/4
Tclk/8
Tclk
Tclk/2
Tclk/4
NOTE:
1. Mid is defined as a voltage level between 1.0 V and 1.8 V for 3 level input functionality. Low is below 0.8 V. High is above 2.0 V.
2. 3V66_1/VCH output frequency is set by the I2C.
3. Frequency of the 48 MHz outputs must be +167 ppm to match USB default.
4. Rref output min = 14.316 MHz, nominal = 14.31818, max = 14.32 MHz.
5. Tclk is a test clock over-driven on the XTAL_In input during test mode.
POWER DOWN MODE
PWRDWN
CPU
CPU
3V66
66BUFF/
3V66
66In/
3V66_5
PCIF/PCI
REF 0
USB/DOT
3V66_1/
VCH
1
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
0
Iref*2
Float
Low
Low
Low
Low
Low
Low
Low
HOST SWING SELECT FUNCTIONS – CK408
MULT 0
BOARD
IMPEDANCE
Iref
IOH
VOH @ 50 W
0
50
Rref = 221.1%
Iref = 5.00 mA
IOH = 4*Iref
1.0 V
1
50
Rref = 475.1%
I ref = 2.32 mA
IOH = 6*Iref
0.7 V
CONDITIONS
CONFIGURATION
LOAD
MIN.
MAX.
IOUT
VDD = 3.3 V
All combinations,
see Table above
Nominal test load for given configuration
–7% of IOH
See Table above
+7% of IOH
See Table above
IOUT
VDD = 3.3 V ±5%
All combinations,
see Table above
Nominal test load for given configuration
–12% of IOH
See Table above
+12% of IOH
See Table above


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