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PCK2001RDB Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCK2001RDB Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 12 page Philips Semiconductors Product specification PCK2001R 14.318 – 133 MHz I2C 1:6 clock buffer 2000 Jul 25 5 AC CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS Tamb = 0°C to +70°C UNIT NOTES MIN TYP9 MAX TP CLK period 1, 6 29.9 30.0 30.2 TH CLK HIGH time 33MHz 2, 6, 8 12.3 14.3 16.3 ns TL CLK LOW time 3, 6, 8 12.1 14.1 16.1 TP CLK period 1, 6 14.9 15.0 15.2 TH CLK HIGH time 66MHz 2, 6, 8 5.6 6.8 8.0 ns TL CLK LOW time 3, 6, 8 5.3 6.5 7.7 TP CLK period 1,6 9.9 10.01 10.2 TH CLK HIGH time 100MHz 2, 6, 8 3.3 4.2 5.1 ns TL CLK LOW time 3, 6, 8 3.2 4.1 5.0 TP CLK period 1, 6 7.4 7.5 7.7 TH CLK HIGH time 133MHz 2, 6, 8 2.6 3.1 3.6 ns TL CLK LOW time 3, 6, 8 2.2 2.7 3.2 TSDRISE Rise time 4, 6, 10 1.5 2.0 4.0 V/ns TSDFALL Fall time 4, 6, 11 1.5 2.5 4.0 V/ns TPLH Buffer LH propagation delay 6, 7 1.0 2.4 3.5 ns TPHL Buffer HL propagation delay 6, 7 1.0 2.6 3.5 ns DUTY CYCLE Output Duty Cycle Measured at 1.5V 5, 6, 7 45 50 55 % TSKW Bus CLK skew 1, 6 150 250 ps TDDSKW Device to device skew 500 ps NOTES: 1. Clock period and skew are measured on the rising edge at 1.5V. 2. TH is measured at 2.4V as shown in Figure 2. 3. TL is measured at 0.4V as shown in Figure 2. 4. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1 mA) JEDEC specification. 5. Duty cycle should be tested with a 50/50% input. 6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature. 7. Input edge rate for these tests must be faster than 1 V/ns. 8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to ensure duty cycle specification is met. 9. All typical values are at VCC = 3.3V and Tamb = 25°C. 10. Typical is measured with MAX (30pF) discrete load. 11. Typical is measured with MIN (20pF) discrete load. |
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