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PCF5083 Datasheet(PDF) 22 Page - NXP Semiconductors |
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PCF5083 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 136 page  1996 Oct 29 22 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 8.3.2.1 Receiver Timing The Receiver Timing is characterized in Table 9. The start and duration times are defined by loading the mentioned registers. Table 9 Receiver Timing (note 1) Notes 1. A minimum delay of 948 quarterbit periods must be programmed between the end of a monitor burst and the start of the next monitor burst, measured from the falling edge of RXON to the next rising edge of RXON. 2. If (MONSTART_REG + 929) > 5000 then the monitor burst ends in the next TDMA timeslot at (MONSTART_REG + 929) − 5000. 3. MODEx_REG[RECRX] enable the generation of Rx burst timing. 4. RXBURSTx_REG (x = 0 to 2) is selected with 2 flags in register MODEx_REG. 5. PDRX1 is not activated during a monitor burst if the MODEx_REG[RXCAL] flag is set. 6. For the three level measurement mode, a second monitor burst can be generated during the TX timeslot. The start position of this burst is then controlled with register TXSTART_REG. Its duration is given from the same register as for the actual monitor burst. 7. If (MONSTART_REG + 929 +RXBURSTx_REG) > 5000 then the monitor burst ends in the next TDMA timeslot at (MONSTART_REG + 929 + RXBURSTx_REG) − 5000. 8. MODEx_REG[RECMON] enable/disable the generation of monitor burst timing. BURST TYPE SIGNAL START (QB)(2) DURATION (BIT) Rx burst(3)(4) RXON RXSTART_REG + 929 = (0 to 127) + 929 RXLENGTHx_REG = (1 to 255) BEN RXSTART_REG + 928 = (0 to 127) + 928 RXLENGTHx_REG +4=(1to 255) + 4 PDRX1(5) RXSTART_REG + 1024 − PDRX1_REG × 32 = (0 to 127) + 1024 − (0 to 31) × 32 to end of RXON PDRX2 RXSTART_REG + 1024 − PDRX2_REG × 32 = (0 to 127) + 1024 − (0 to 31) × 32 to end of RXON PDSYN RXSTART_REG + 1024 − PDSYN_REG × 32 = (0 to 127) + 1024 − (0 to 31) × 32 to end of RXON MON burst(6)(7)(8) RXON MONSTART_REG + 929 = (0 to 4999) + 929 RXLENGTHx_REG = (1 to 255) BEN MONSTART_REG + 928 = (0 to 4999) + 928 RXLENGTHx_REG +4=(1to 255) + 4 PDRX1(5) MONSTART_REG + 1024 − PDRX1_REG × 32 = (0 to 4999) + 1024 − (0 to 31) × 32 to end of RXON PDRX2 MONSTART_REG + 1024 − PDRX2_REG × 32 = (0 to 4999) + 1024 − (0 to 31) × 32 to end of RXON PDSYN MONSTART_REG + 1024 − PDSYN_REG × 32 = (0 to 4999) + 1024 − (0 to 31) × 32 to end of RXON |
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Similar Description - PCF5083 |
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