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MC33999 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

Part No. MC33999
Description  16-Output Switch with SPI and PWM Control
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MC33999 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33999
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V
≤ SO
PWR ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values noted reflect the approximate parameter means at VPWR = 13 V, TA = 25°C under nominal conditions
unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Slew Rate
RL = 60 Ω
(15)
SR
1.0
2.0
10
V/
µs
Output Turn ON Delay Time (16)
T DLY(ON)
1.0
2.0
10
µs
Output Turn OFF Delay Time (16)
T DLY(OFF)
1.0
4.0
10
µs
Output ON Short Fault Disable Report Delay (17)
T DLY(SHORT)
100
450
µs
Output OFF Open Fault Delay Time (17)
T DLY(OPEN)
100
450
µs
Output PWM Frequency
T FREQ
2.0
kHz
DIGITAL INTERFACE TIMING (23)
Required Low State Duration on VPWR for Reset
VPWR ≤ 0.2 V
(18)
TRST
10
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
T LEAD
100
ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
TLAG
50
ns
SI to Falling Edge of SCLK (Required Setup Time)
TSI(SU)
16
ns
Falling Edge of SCLK to SI (Required Setup Time)
TSI(HOLD)
20
ns
SI, CS, SCLK Signal Rise Time (19)
TR(SI)
5.0
ns
SI, CS, SCLK Signal Fall Time (19)
TF(SI)
5.0
ns
Time from Falling Edge of CS to SO Low Impedance (20)
TSO(EN)
50
ns
Time from Rising Edge of CS to SO High Impedance (21)
TSO(DIS)
50
ns
Time from Rising Edge of SCLK to SO Data Valid (22)
TVALID
25
80
ns
Notes
15.
Output slew rate measured across a 60
Ω resistive load.
16.
Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.
17.
Duration of fault before fault bit is set. Duration between access times must be greater than 450
µs to read faults.
18.
This parameter is guaranteed by design but is not production tested.
19.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20.
Time required for valid output status data to be available on SO pin.
21.
Time required for output status data to be terminated at SO pin.
22.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
23.
This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.


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