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PCF5001 Datasheet(PDF) 22 Page - NXP Semiconductors |
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PCF5001 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 44 page  1997 Mar 04 22 Philips Semiconductors Product specification POCSAG Paging Decoder PCF5001 Table 8 Numeric format to ASCII conversion 4-BIT BLOCK CHARACTER 7-BIT BLOCK LSB MSB LSB MSB 0000 ‘0’ 0000110 1000 ‘1’ 1000110 0100 ‘2’ 0100110 1100 ‘3’ 1100110 0010 ‘4’ 0010110 1010 ‘5’ 1010110 0110 ‘6’ 0110110 1110 ‘7’ 1110110 0001 ‘8’ 0001110 1001 ‘9’ 1001110 0101 ‘*’ 0101010 1101 ‘U’ 1010101 0011 ‘ ’ 0000010 1011 ‘ −’ 1 011010 0111 ‘]’ 1011101 1111 ‘[’ 1101100 7.17 Memory Organization The PCF5001 POCSAG decoder contains non-volatile EEPROM memory to store four user addresses, two frame numbers and specially programmed function bits (SPF01 to SPF32) for decoder application configuration. The EEPROM is organized as three arrays of 38 bits each as shown in Fig.17. A user address (or RIC) in POCSAG code comprises of 21 bits, but the three least significant bits are coded in the frame number and therefore not explicitly transmitted. In the PCF5001, addresses A/B and C/D must share the same frame number: addresses A and B reside in frame FR1 (FR10, FR11 and FR12), addresses C and D reside in frame FR2 (FR20, FR21 and FR22). Figure 18 shows an example of decimal address to EEPROM content conversion. Each address must be explicitly enabled by resetting of the associated enable bit. |
Similar Part No. - PCF5001 |
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Similar Description - PCF5001 |
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