PSD835G2V-90U datasheet(5/118 Pages) STMICROELECTRONICS

Part #	PSD835G2V-90U

Description	Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit 256 Kbit dual Flash memories and 64 Kbit SRAM

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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5 / 118 page

PSD835G2V

Contents

5/118

17.4

PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

17.5

Address out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

17.6

Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17.7

Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17.8

Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17.9

JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17.10 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17.11 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17.12 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

17.13 Drive Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

17.14 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.16 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.18 OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

17.21 Ports A,B and C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . 80

17.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

17.23 Port E – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.24 Port F – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

17.25 Port G – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

18

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

18.1

Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 85

18.1.1

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

18.2

Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

18.3

PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

18.3.1

SRAM Standby mode (battery backup) . . . . . . . . . . . . . . . . . . . . . . . . . 87

18.4

PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

18.5

Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

18.6

Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

19

Reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . 89

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