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PCF1179CU Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCF1179CU Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 20 page  1997 Apr 16 6 Philips Semiconductors Product specification 4-digit duplex LCD car clock PCF1179C 12/24-hour mode Operation in 12-hour or 24-hour mode is selected by connecting MODE to VDD or VSS respectively. If MODE is left open-circuit and a reset occurs, the mode will change from 12-hour to 24-hour mode or vice versa. Power-on After connecting the supply, the start-up mode is: MODE connected to VDD: 12-hour mode, 1:00 AM. MODE connected to VSS: 24-hour mode, 0:00. MODE left open-circuit: 24-hour mode, 0:00 or 1:00. Colon If FLASH is connected to VDD the colon pulses at 1 Hz. If FLASH is connected to VSS the colon is static. Time setting Switch inputs S1 and S2 have a pull-up resistor to facilitate the use of single-pole, single-throw contacts. A debounce circuit is incorporated to protect against contact bounce and parasitic voltages. Set enable Inputs S1 and S2 are enabled by connecting ENABLE to VDD or disabled by connecting to VSS. Set hours When S1 is connected to VSS the hours displayed advances by one and after one second continues with four advances per second until S1 is released (auto-increment). An overflow in the hour counter must not have an influence on the minute counter. Set minutes When S2 is connected to VSS the time displayed in minutes advances by one and after one second continues with four advances per second until S2 is released (auto-increment). In addition to minute correction, the seconds counter is reset to zero. An overflow in the minute counter must not have an influence on the hour counter. Segment test/reset When S1 and S2 are connected to VSS, all LCD segments are switched ON. Releasing switches S1 and S2 resets the display. No reset occurs when DATA is connected to VSS (overlapping S1 and S2). Test mode When TS is connected to VDD, the device is in normal operating mode. When connecting TS to VSS all counters (seconds, minutes and hours) are stopped, allowing quick testing of the display via S1 and S2 (debounce and auto-increment times are 64 times faster). TS has a pull-up resistor but for reasons of safety it should be connected to VDD. EEPROM VPP has a pull-up resistor but for reasons of safety it should be connected to VDD. LCD voltage programming To enable LCD voltage programming, SEL is set to open-circuit and a level of VDD − 5 V is applied to VPP (see Fig.6). The first pulse (tE) applied to the DATA input clears the EEPROM to give the lowest voltage output. Further pulses (tL) will increment the output voltage by steps of typically 150 mV (Tamb =25 °C). For programming, measure VDD − VSS and apply a store pulse (tW) when the required value is reached. If the maximum number of steps (n = 31) is reached and an additional pulse is applied the voltage will return to the lowest value. Time calibration To compensate for the tolerance in the quartz crystal frequency which has been positively offset (nominal deviation +60 × 10−6 by capacitors at the oscillator input and output, a number (n) of 262144 Hz pulses are inhibited every second of operation. |
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Similar Description - PCF1179CU |
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