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PCD5042 Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCD5042 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 28 page 1996 Oct 31 6 Philips Semiconductors Objective specification DECT burst mode controller PCD5042 Notes 1. Un-referenced pins for the LQFP80 package are not connected. FS3, FS4 and the comparator signals are only available in the LQFP80 package. 2. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected. R_ENABLE 54 64 O receiver enable (active LOW) R_POWER_DWN 55 65 O receiver power-down COMP_NE − 66 I digital input comparator not_enable (active LOW) SLICE_CTR 56 67 O slice time constant control COMP_OUT − 68 O digital comparator output VDD3 57 69 P positive supply 3 VSS5 58 70 P negative supply 5 COMP_INM − 71 I analog comparator input negative VREF 59 72 I reference input for the A/D converter COMP_INP − 73 I analog input positive VDD(RAM) 60 74 P power supply for data RAM SYNCPORT 61 76 I/O in the base station the signal is the SYNCPORT RESET 62 77 I BMC master reset signal MEM_SEL 63 78 I selects PCC program memory at microcontroller interface EN_WATCHDOG 64 79 I enable watchdog input; when HIGH, the watchdog timer of the BMC is enabled SYMBOL PIN TYPE(2) DESCRIPTION QFP64 LQFP80(1) |
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