SMJ626162

524288 BY 16-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SGMS737C – JULY 1997 – REVISED MARCH 1999

18

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level is changed

valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also

valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are

specified as consecutive commands for the same bank unless otherwise noted.

Tester Pin

Electronics

1.4 V

CL = 50 pF

IOH

Output

Under

Test

50

Ω

NOTE A: Series termination resistors may be used on test

hardware for output impedance matching purposes.

(see Note A)

IOL

Figure 8. LVTTL-Load Circuit

tCK

CLK

tT

tT

tDH, tAH, tCH, tCEH

tT

tDH, tAH, tCH, tCEH

tT

tDS, tAS, tCS, tCES, tCESP

tCKL

DQ, A0–A11, CS, RAS,

CAS, W, DQMx, CKE

DQ, A0–A11, CS, RAS,

CAS, W, DQMx, CKE

tCKH

tDS, tAS, tCS, tCES

Figure 9. Input-Attribute Parameters