Philips Semiconductors

Product specification

PCA9544

1999 Oct 07

9

AC CHARACTERISTICS

SYMBOL

PARAMETER

STANDARD-MODE

UNIT

MIN

MAX

MIN

MAX

ns

SCL clock frequency

0

100

0

400

KHz

Bus free time between a STOP and START condition

4.7

–

1.3

–

µs

Hold time (repeated) START condition

After this period, the first clock pulse is generated

4.0

–

0.6

–

µs

LOW period of the SCL clock

4.7

–

1.3

–

µs

HIGH period of the SCL clock

4.0

–

0.6

–

µs

Set-up time for a repeated START condition

4.7

–

0.6

µs

Data hold time:

for CBUS compatible masters

5.0

–

–

–

µs

–

µs

Data set-up time

250

–

–

ns

Set-up time for STOP condition

–

1000

–

300

ns

Rise time of both SDA and SCL signals

–

300

–

300

ns

Fall time of both SDA and SCL signals

4.0

–

0.6

–

µs

Capacitive load for each bus line

400

–

400

pF

INT

INTn to INT active valid time

4

4

µs

INTn to INT inactive delay time

2

2

µs

LOW level pulse width rejection or INTn inputs

1

1

ns

HIGH level pulse width rejection or INTn inputs

500

500

ns

NOTES:

1. Pass gate propagation delay is calculated from the 20

the undefined region of the falling edge of SCL.

will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period

P

P

S

Sr

SDA

SCL

SU00645