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PCA9544 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCA9544 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 12 page Philips Semiconductors Product specification PCA9544 4-channel I2C multiplexer and interrupt controller 1999 Oct 07 9 AC CHARACTERISTICS SYMBOL PARAMETER STANDARD-MODE I2C-BUS FAST-MODE I2C-BUS UNIT MIN MAX MIN MAX tpd Propagation delay from SDA to SDn or SCL to SCn 0.31 0.31 ns fSCL SCL clock frequency 0 100 0 400 KHz tBUF Bus free time between a STOP and START condition 4.7 – 1.3 – µs tHD:STA Hold time (repeated) START condition After this period, the first clock pulse is generated 4.0 – 0.6 – µs tLOW LOW period of the SCL clock 4.7 – 1.3 – µs tHIGH HIGH period of the SCL clock 4.0 – 0.6 – µs tSU:STA Set-up time for a repeated START condition 4.7 – 0.6 µs Data hold time: tHD:DAT for CBUS compatible masters 5.0 – – – µs for I2C-bus devices 02 – 02 0.93 µs tSU:DAT Data set-up time 250 – 1004 – ns tSU:STO Set-up time for STOP condition – 1000 – 300 ns tr Rise time of both SDA and SCL signals – 300 – 300 ns tf Fall time of both SDA and SCL signals 4.0 – 0.6 – µs Cb Capacitive load for each bus line 400 – 400 pF INT tiv INTn to INT active valid time 4 4 µs tir INTn to INT inactive delay time 2 2 µs Lpwr LOW level pulse width rejection or INTn inputs 1 1 ns Hpwr HIGH level pulse width rejection or INTn inputs 500 500 ns NOTES: 1. Pass gate propagation delay is calculated from the 20 Ω typical RON and and the 15pF load capacitance. 2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 5. Cb = total capacitance of one bus line in pF. tSP tBUF tHD;STA P P S tLOW tR tHD;DAT tF tHIGH tSU;DAT tSU;STA Sr tHD;STA tSU;STO SDA SCL SU00645 Figure 8. Definition of timing on the I2C-bus |
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