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SN74LVC2G04DCKRG4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVC2G04DCKRG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page www.ti.com FEATURES 3 2 4 6 1 1A 1Y 2Y GND 2A DBV PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) DCK PACKAGE (TOP VIEW) 3 2 4 6 1 1A 1Y 2Y GND 2A 3 2 4 6 1 1A 1Y 2Y GND 2A 1A 2A 1Y 2Y GND DRL PACKAGE (TOP VIEW) See mechanical drawings for dimensions. 1 4 2 3 6 VCC VCC VCC 5 VCC 5 5 5 DESCRIPTION/ORDERING INFORMATION SN74LVC2G04 DUAL INVERTER GATE SCES195L – APRIL 1999 – REVISED JANUARY 2007 • Available in the Texas Instruments • I off Supports Partial-Power-Down Mode NanoFree™ Package Operation • Supports 5-V V CC Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22 • Max t pd of 4.1 ns at 3.3 V – 2000-V Human-Body Model (A114-A) • Low Power Consumption, 10-µA Max I CC – 200-V Machine Model (A115-A) • ±24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101) • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, TA = 25°C • Typical V OHV (Output VOH Undershoot) >2 V at V CC = 3.3 V, TA = 25°C This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G04 performs the Boolean function Y = A. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP Reel of 3000 SN74LVC2G04YZPR _ _ _CC_ (Pb-free) Reel of 3000 SN74LVC2G04DBVR SOT (SOT-23) – DBV C04_ –40 °C to 85°C Reel of 250 SN74LVC2G04DBVT Reel of 3000 SN74LVC2G04DCKR SOT (SC-70) – DCK CC_ Reel of 250 SN74LVC2G04DCKT SOT (SOT-563) – DRL Reel of 4000 SN74LVC2G04DRLR CC_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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