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SN74AUP1G74 Datasheet(PDF) 3 Page - Texas Instruments

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Part No. SN74AUP1G74
Description  LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74AUP1G74 Datasheet(HTML) 3 Page - Texas Instruments

 
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TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
CLR
CLK
D
PRE
Q
Q
C
6
2
7
3
5
1
Absolute Maximum Ratings
(1)
SN74AUP1G74
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES644A – MARCH 2006 – REVISED SEPTEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range(2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
4.6
V
VO
Output voltage range in the high or low state(2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
DCT package
220
θ
JA
Package thermal impedance(3)
DCU package
227
°C/W
YEP/YZP package
102
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51-7.
3
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