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SN54ALS161B Datasheet(PDF) 12 Page - Texas Instruments

Part No. SN54ALS161B
Description  SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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SN54ALS161B Datasheet(HTML) 12 Page - Texas Instruments

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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A – DECEMBER 1994 – REVISED JULY 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit
(see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
’ALS161B, ’AS161, ’ALS163B, and ’AS163 devices count in binary. When additional stages are added, the fmax
decreases in Figure 2, but remains unchanged in Figure 3.
Figure 2. Ripple-Mode Carry Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Count (H)
Disable (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N – 2) + (ENT tsu)
Figure 3. Carry Look-Ahead Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENP tsu)


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