www.ti.com

GSCLK

BLANK

GSPWM

Cyclen

1

2

3

1

GSPWM

Cyclen+1

OUT0

OUT1

OUT15

XERR

4096

(Current)

(Current)

(Current)

SERIAL DATA TRANSFER RATE

f

(GSCLK) +

4096

f

(update)

f

(SCLK) +

193

f

(update)

n

(10)

TLC5945

SLVS755 – MARCH 2007

each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values

are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and

completes the grayscale PWM cycle (see Figure 15). When the counter reaches a count of FFFh, the counter

stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets

the counter to zero.

Figure 15. Grayscale PWM Cycle Timing Chart

Figure 16 shows a cascading connection of n TLC5945 devices connected to a controller, building a basic

module of an LED display system. There is no TLC5945 limitation to the maximum number of ICs that can be

cascaded. The maximum number of cascading TLC5945 devices depends on the application system and is in

the range of 40 devices. Equation 10 calculates the minimum frequency needed:

where:

n: number cascaded of TLC5945 device

18

Submit Documentation Feedback