9

FN9253.1

August 7, 2006

written as:

Where:

overcurrent setpoint

the ISEN pin

pin that will activate the OCP circuit

Overvoltage Protection

When an OVP fault is detected, the PGOOD pin will pull

down to 60

Ω and latch-off the converter. The OVP fault will

remain latched until the EN pin has been pulled below the

The OVP fault detection circuit triggers after the voltage

across the FB and GND pins has increased above the rising

latched-off in response to an OVP fault, the LG gate-driver

output will retain the ability to toggle the low-side MOSFET

on and off, in response to the output voltage transversing the

Undervoltage Protection

When a UVP fault is detected, the PGOOD pin will pull down

to 95

Ω and latch-off the converter. The fault will remain

latched until the EN pin has been pulled below the falling EN

detection circuit triggers after the voltage across the FB and

Over-Temperature

When the temperature of the ISL6269A increases above the

state that suspends the PWM , forcing the LG and UG

gate-driver outputs low. The status of the PGOOD pin does

not change nor does the converter latch-off. The PWM

remains suspended until the IC temperature falls below the

operation resumes. The OTP state can be reset if the EN pin

V

during OTP. It is likely that the IC will detect an UVP fault

because in the absence of PWM, the output voltage

converter. The UVP fault will remain latched until the EN pin

has been pulled below the falling EN threshold voltage

Programming the Output Voltage

When the converter is in regulation there will be 600mV from

the FB pin to the GND pin. Connect a two-resistor voltage

divider across the VO pin and the GND pin with the output

node connected to the FB pin. Scale the voltage-divider

network such that the FB pin is 600mV with respect to the

GND pin when the converter is regulating at the desired

output voltage. The output voltage can be programmed from

600mV to 3.3V.

Programming the output voltage is written as:

Where:

between the FB pin and the GND pin

from the FB pin to the VO pin. In addition to setting the

output voltage, this resistor is part of the loop

compensation network

connects from the FB pin to the GND pin

Programming the PWM Switching Frequency

The ISL6269A does not use a clock signal to produce PWM.

GND pin. The approximate PWM switching frequency is

written as:

Where:

I

•

I

()

•

=

(EQ. 3)

(EQ. 4)

R

SEN

I

FL

I

PP

2

---------

+

⎝⎠

⎛⎞

OC

SP

•

r

DS on

()

•

I

OC

--------------------------------------------------------------------------

=

V

REF

V

OUT

R

BOTTOM

R

TOP

R

BOTTOM

+

---------------------------------------------------

•

=

(EQ. 5)

R

BOTTOM

V

•

TOP

V

OUT

V

REF

–

-------------------------------------

=

(EQ. 6)

F

SW

1

KR

FSET

⋅

---------------------------

=

(EQ. 7)

R

FSET

1

KF

SW

•

--------------------

=

(EQ. 8)

ISL6269A