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ISL6567 Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6567 Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 26 page 10 FN9243.2 March 20, 2007 INTERLEAVING The switching of each channel in a ISL6567-based converter is timed to be symmetrically out of phase with the other channel. As a result, the two-phase converter has a combined ripple frequency twice the frequency of one of its phases. In addition, the peak-to-peak amplitude of the combined inductor currents is proportionately reduced. Increased ripple frequency and lower ripple amplitude generally translate to lower per-channel inductance and/or lower total output capacitance for any given set of performance specification. Figure 3 illustrates the additive effect on output ripple frequency. The two channel currents (IL1 and IL2), combine to form the AC ripple current and the DC load current. The ripple component has two times the ripple frequency of each individual channel current. To understand the reduction of ripple current amplitude in the multi-phase circuit, examine the equation representing an individual channel’s peak-to-peak inductor current. VIN and VOUT are the input and output voltages, respectively, L is the single-channel inductor value, and fS is the switching frequency. The output capacitors conduct the ripple component of the inductor current. In the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. Peak-to-peak ripple current decreases by an amount proportional to the number of channels. Output-voltage ripple is a function of capacitance, capacitor equivalent series resistance (ESR), and inductor ripple current. Reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors (should output high-frequency ripple be an important design parameter). Another benefit of interleaving is the reduction of input ripple current. Input capacitance is determined in a large part by the maximum input ripple current. Multi-phase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. The example in Figure 4 illustrates input currents from a two-phase converter combining to reduce the total input ripple current. Figure 28, part of the section entitled Input Capacitor Selection, can be used to determine the input-capacitor RMS current based on load current and duty cycle. The figure is provided as an aid in determining the optimal input capacitor solution. PWM OPERATION One switching cycle for the ISL6567 is defined as the time between consecutive PWM pulse terminations (turn-off of the upper MOSFET on a channel). Each cycle begins when a switching clock signal commands the upper MOSFET to go off. The other channel’s upper MOSFET conduction is terminated 1/2 of a cycle later. Once a channel’s upper MOSFET is turned off, the lower MOSFET remains on for a minimum of 1/3 cycle. This forced off time is required to assure an accurate current sample. Following the 1/3-cycle forced off time, the controller enables the upper MOSFET output. Once enabled, the upper MOSFET output transitions high when the sawtooth signal crosses the adjusted error-amplifier output signal, as illustrated in Figure 2. Just prior to the upper drive turning FIGURE 3. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR 2-PHASE CONVERTER PWM2 PWM1 IL2 IL1 IL1 + IL2 I LPP , V IN V OUT – () V OUT ⋅ Lf S V ⋅ IN ⋅ ---------------------------------------------------------- = I PP V IN NV OUT ⋅ – () V OUT ⋅ Lf S V ⋅ IN ⋅ -------------------------------------------------------------------- = FIGURE 4. INPUT CAPACITOR CURRENT AND INDIVIDUAL CHANNEL CURRENTS IN A 2-PHASE CONVERTER Q1 D-S CURRENT Q3 D-S CURRENT CIN CURRENT ISL6567 ISL6567 |
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