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ISL6310 Datasheet(PDF) 18 Page  Intersil Corporation 

ISL6310 Datasheet(HTML) 18 Page  Intersil Corporation 
18 / 27 page 18 FN9209.3 December 12, 2006 When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. Once the lower MOSFET begins conducting, the current in the upper MOSFET falls to zero as the current in the lower MOSFET ramps up to assume the full inductor current. In Equation 16, the required time for this commutation is t1 and the approximated associated power loss is PUP,1. At turn on, the upper MOSFET begins to conduct and this transition occurs over a time t2. In Equation 17, the approximate power loss is PUP,2. A third component involves the lower MOSFET reverse recovery charge, Qrr. Since the inductor current has fully commutated to the upper MOSFET before the lower MOSFET body diode can recover all of Qrr, it is conducted through the upper MOSFET across VIN. The power dissipated as a result is PUP,3. Finally, the resistive part of the upper MOSFET is given in Equation 19 as PUP,4. The total power dissipated by the upper MOSFET at full load can now be approximated as the summation of the results from Equations 16, 17, 18 and 19. Since the power equations depend on MOSFET parameters, choosing the correct MOSFETs can be an iterative process involving repetitive solutions to the loss equations for different MOSFETs and different switching frequencies. Package Power Dissipation When choosing MOSFETs it is important to consider the amount of power being dissipated in the integrated drivers located in the controller. Since there are a total of two drivers in the controller package, the total power dissipated by both drivers must be less than the maximum allowable power dissipation for the QFN package. Calculating the power dissipation in the drivers for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125°C. The maximum allowable IC power dissipation for the 5x5 QFN package is approximately 4W at room temperature. See “Layout Considerations” on page 24. paragraph for thermal transfer improvement suggestions. When designing the ISL6310 into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, PQg_TOT, due to the gate charge of MOSFETs and the integrated driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 20 and 21, respectively. In Equations 20 and 21, PQg_Q1 is the total upper gate drive power loss and PQg_Q2 is the total lower gate drive power loss; the gate charge (QG1 and QG2) is defined at the particular gate to source drive voltage PVCC in the corresponding MOSFET data sheet; IQ is the driver total quiescent current with no load at both drive outputs; NQ1 and NQ2 are the number of upper and lower MOSFETs per phase, respectively; NPHASE is the number of active phases. The IQ*VCC product is the quiescent power of the controller without capacitive load and is typically 75mW at 300kHz. The total gate drive power losses are dissipated among the resistive components along the transition path and in the bootstrap diode. The portion of the total power dissipated in the controller itself is the power dissipated in the upper drive path resistance, PDR_UP, the lower drive path resistance, PDR_LOW, and in the boot strap diode, PBOOT. The rest of the power will be dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of the MOSFETs. Figures 15 and 16 show the typical upper and lower gate drives turnon transition path. The total power dissipation in the controller itself, PDR, can be roughly estimated as: P UP 1 , V IN I M N  I PP 2  + ⎝⎠ ⎛⎞ t 1 2  ⎝⎠ ⎜⎟ ⎛⎞ F SW ⋅⋅ ⋅ ≈ (EQ. 16) P UP 2 , V IN I M N  I PP 2  – ⎝⎠ ⎜⎟ ⎛⎞ t 2 2  ⎝⎠ ⎜⎟ ⎛⎞ F SW ⋅⋅ ⋅ ≈ (EQ. 17) P UP 3 , V IN Q rr FSW ⋅⋅ = (EQ. 18) P UP 4 , r DS ON () I M N  ⎝⎠ ⎜⎟ ⎛⎞ 2 d ⋅ I PP 2 12  + ⋅ ≈ (EQ. 19) P Qg_TOT P Qg_Q1 P Qg_Q2 I Q VCC ⋅ ++ = (EQ. 20) P Qg_Q1 3 2  Q G1 PVCC FSW NQ1 NPHASE ⋅⋅ ⋅ ⋅ ⋅ = P Qg_Q2 Q G2 PVCC FSW NQ2 NPHASE ⋅⋅ ⋅ ⋅ = I DR 3 2  Q G1 N ⋅ Q1 ⋅ Q G2 NQ2 ⋅ + ⎝⎠ ⎛⎞ N PHASE FSW I Q + ⋅⋅ = (EQ. 21) P DR P DR_UP P DR_LOW P BOOT I Q VCC • () ++ + = (EQ. 22) P DR_UP R HI1 R HI1 R EXT1 +  R LO1 R LO1 R EXT1 +  + ⎝⎠ ⎜⎟ ⎛⎞ P Qg_Q1 3  ⋅ = P DR_LOW R HI2 R HI2 R EXT2 +  R LO2 R LO2 R EXT2 +  + ⎝⎠ ⎜⎟ ⎛⎞ P Qg_Q2 2  ⋅ = R EXT1 R G1 R GI1 N Q1  + = R EXT2 R G2 R GI2 N Q2  + = P BOOT P Qg_Q1 3  = ISL6310 
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