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ISL6310 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6310 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 FN9209.3 December 12, 2006 Timing Diagram Simplified Power System Diagram Functional Pin Description VCC (Pin 3) Bias supply for the IC’s small-signal circuitry. Connect this pin to a +5V supply and locally decouple using a quality 1.0 μF ceramic capacitor. PVCC (Pin 15) Power supply pin for the MOSFET drive. This pin can be connected to any voltage from +5V to +12V, depending on the desired MOSFET gate drive level. GND (Pin 33) Bias and reference ground for the IC. ENLL (Pin 20) This pin is a threshold sensitive (approximately 0.66V) enable input for the controller. Held low, this pin disables controller operation. Pulled high, the pin enables the controller for operation. FS (Pin 29) A resistor, placed from FS to ground, will set the switching frequency. Refer to Equation 33 and Figure 24 for proper resistor calculation. 2PH (Pin 31) This pin is used to choose between single or two phase operation. Tying this pin to VCC allows for 2-Phase operation. Tying the 2PH pin to GND causes the controller to operate in a single phase mode. REF0 and REF1 (Pins 30, 21) These pins make up the 2-Bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL6310 decodes these inputs to establish UGATE LGATE tFLGATE tPDHUGATE tRUGATE tFUGATE tPDHLGATE tRLGATE CHANNEL1 +5VIN VOUT Q1 Q2 ISL6310 DAC CHANNEL2 Q3 Q4 +12VIN ENLL PGOOD 2 REF0,REF1 OVP ISL6310 |
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