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INA270AIDG4 Datasheet(PDF) 11 Page - Burr-Brown (TI) |
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INA270AIDG4 Datasheet(HTML) 11 Page - Burr-Brown (TI) |
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11 / 17 page  www.ti.com Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS SHUTDOWN RFI/EMI 0.48 0.48 0.40 0.36 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 0 0 2 4 6 8 10 12 14 16 18 20 22 V (mV) SENSE 24 INA271V OUT Limit (1) V CM2 V CM1 V CM3 V CM4 V ,V CM2 CM3 CM4 ,andV illustratethevariance fromparttopartoftheV thatcancause CM maximumV withV <20mV. OUT SENSE V limitatV =0mV, OUT SENSE 0 V £ CM1 S £ V NOTE:(1)INA271V Limit=0.4V.INA270V Limit=0.28V. OUT OUT Ideal INA270 INA271 SBOS381A – FEBRUARY 2007 – REVISED APRIL 2007 This region of operation is the least accurate for the The INA270 and INA271 do not provide a shutdown INA270 family. To achieve the wide input pin; however, because they consume a quiescent common-mode voltage range, these devices use two current less than 1mA, they can be powered by op amp front ends in parallel. One op amp front end either the output of logic gates or by transistor operates in the positive input common-mode voltage switches to supply power. Driving the gate low shuts range, and the other in the negative input region. For down the INA270–INA271. Use a totem-pole output this case, neither of these two internal amplifiers buffer or gate that can provide sufficient drive along dominates and overall loop gain is very low. Within with 0.1 µF bypass capacitor, preferably ceramic with this region, VOUT approaches voltages close to linear good high-frequency characteristics. This gate operation levels for Normal Case 2. should have a supply voltage of 3V or greater because the INA270 and INA271 require a minimum This deviation from linear operation becomes supply greater than 2.7V. In addition to eliminating greatest the closer VSENSE approaches 0V. Within quiescent current, this gate also turns off the 10 µA this region, as VSENSE approaches 20mV, device bias current present at each of the inputs. Note that operation is closer to that described by Normal Case the IN+ and IN– inputs are able to withstand full 2. Figure 18 illustrates this behavior for the INA271. common-mode voltage under all powered and The VOUT maximum peak for this case is determined under-powered conditions. An example shutdown by maintaining a constant VS, setting VSENSE = 0mV, circuit is illustrated in Figure 19. and sweeping VCM from 0V to VS. The exact VCM at which VOUT peaks during this case varies from part to part. The maximum peak voltage for the INA270 is 0.28V; for the INA271, the maximum peak voltage is Attention to good layout practices is always 0.4V. recommended. Keep traces short and, when possible, use a printed circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Small ceramic capacitors placed directly across amplifier inputs can reduce RFI/EMI sensitivity. PCB layout should locate the amplifier as far away as possible from RFI sources. Sources can include other components in the same system as the amplifier itself, such as inductors (particularly switched inductors handling a lot of current and at high frequencies). RFI can generally be identified as a variation in offset voltage or dc signal levels with changes in the interfering RF signal. If the amplifier cannot be located away from sources of radiation, shielding may be needed. Twisting wire input leads makes them more resistant to RF fields. The difference in input pin location of the INA270 and INA271 versus the INA193–INA198 may provide different EMI performance. Figure 18. Example for Low VSENSE Case 2 (INA271, Gain = 20) 11 Submit Documentation Feedback |
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