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ADS5547 Datasheet(PDF) 4 Page - Texas Instruments

Part No. ADS5547
Description  14-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5547 Datasheet(HTML) 4 Page - Texas Instruments

 
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ELECTRICAL CHARACTERISTICS
ADS5547
SLWS192A – NOVEMBER 2006 – REVISED MAY 2007
Typical values are at 25
°C, min and max values are across the full temperature range T
MIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 V
PP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0 db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
bits
ANALOG INPUT
Differential input voltage range
2
VPP
Differential input capacitance
7
pF
Analog input bandwidth
800
MHz
Analog input common mode current
342
µA
(per input pin)
REFERENCE VOLTAGES
V(REFB)
Internal reference bottom voltage
Internal reference mode
0.5
V
V(REFT)
Internal reference top voltage
Internal reference mode
2.5
V
∆V
(REF)
Internal reference error
V(REFT) - V(REFB)
-60
± 25
60
mV
VCM
Common mode output voltage
Internal reference mode
1.5
V
VCM output current capability
Internal reference mode
±4
mA
DC ACCURACY
No Missing Codes
Assured
DNL
Differential non-linearity
-0.95
0.5
2.5
LSB
INL
Integral non-linearity
-5
3.5
5
LSB
Offset error
-10
5
10
mV
Offset temperature coefficient
0.002
ppm/
°C
Gain error due to internal reference
(
∆V
(REF) / 2.0V) %
-3
±1
3
%FS
error alone
Gain error excluding internal reference
-2
± 0.5
2
%FS
error(1)
Gain temperature coefficient
0.01
∆%/°C
PSRR
DC Power supply rejection ratio
0.6
mV/V
POWER SUPPLY
I(AVDD)
Analog supply current
306
mA
LVDS mode, IO = 3.5 mA,
66
mA
RL = 100 Ω, CL = 5 pF
I(DRVDD)
Digital supply current
CMOS mode, FIN = 2.5 MHz,
47
mA
CL = 5 pF
ICC
Total supply current
LVDS mode
372
mA
Total power dissipation
LVDS mode
1.23
1.375
W
Standby power
In STANDBY mode with clock stopped
100
150
mW
Clock stop power
With input clock stopped
100
150
mW
(1)
Gain error is specified from design and characterization; it is not tested in production.
4
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