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ADS5527 Datasheet(PDF) 6 Page - Texas Instruments

Part No. ADS5527
Description  12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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ADS5527 Datasheet(HTML) 6 Page - Texas Instruments

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ADS5527
SLWS196A – DECEMBER 2006 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25
°C, min and max values are across the full temperature range T
MIN = –40°C to TMAX = 85°C,
AVDD = DRVDD = 3.3 V, sampling rate = 210 MSPS, sine wave input clock, 1.5 V
PP differential clock amplitude, 50% clock
duty cycle, –1 dBFS differential analog input, internal reference mode, 0-db gain, DDR LVDS data output (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FIN = 20 MHz
86
FIN = 70 MHz
75
84
FIN = 100 MHz
78
FIN = 170 MHz
79
0 dB gain, 2 VPP FS
75
HD3
Third harmonic
FIN = 230 MHz
dBc
3 dB gain, 1.4 VPP FS
78
0 dB gain, 2 VPP FS
74
FIN = 300 MHz
3 dB gain, 1.4 VPP FS
76
0 dB gain, 2 VPP FS
68
FIN = 400 MHz
3 dB gain, 1.4 VPP FS
70
FIN = 20 MHz
95
FIN = 70 MHz
92
FIN = 100 MHz
92
Worst harmonic (other than HD2, HD3)
FIN = 170 MHz
90
dBc
FIN = 230 MHz
90
FIN = 300 MHz
88
FIN = 400 MHz
87
FIN = 20 MHz
83
FIN = 70 MHz
73
82
FIN = 100 MHz
76
THD
Total harmonic distortion
FIN = 170 MHz
77
dBc
FIN = 230 MHz
73
FIN = 300 MHz
72
FIN = 400 MHz
65
ENOB
Effective number of bits
FIN = 70 MHz
10.9
11.4
bits
FIN1 = 50.03 MHz, FIN2 = 46.03 MHz,
91
-7 dBFS each tone
IMD
Two-tone intermodulation distortion
dBFS
FIN1 = 190.1 MHz, FIN2 = 185.02 MHz,
86
-7 dBFS each tone
PSRR
AC power supply rejection ratio
30 MHz, 200 mVPP signal on 3.3-V supply
35
dBc
Recovery to 1% (of final value) for 6-dB overload
Clock
Voltage overload recovery time
1
with sine-wave input at Nyquist frequency
cycles
6
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