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ISL6422EVEZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6422EVEZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 19 page  11 FN9190.1 April 10, 2007 Current Limiting The dynamic back current limit block has five thresholds that can be selected by the following bits of the SR. • ISEL1H and ISEL2H • ISEL1L and ISEL2L • ISEL1R and ISEL2R See Table 8 and Table 9 for threshold selection using these bits. The DCL1 and DCL2 bits have to be set to low for this mode of operation. In this mode, the overcurrent protection circuit works dynamically 23µs after an overload is detected, and the output is shutdown for a time tOFF, typically 900ms. Simultaneously, the OLF1 or OLF2 bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time tON = 20ms. During tON, the device output will be current limited to a 990mA typ level. If the overload is still detected, the protection circuit will cycle again through tOFF and tON. At the end of a full tON, in which no overload is detected, normal operation is resumed and the OLF1 or OLF2 bit is reset to LOW. Typical tON +tOFF time is 920ms as determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF1 or OLF2 bit goes HIGH when the peak current sense threshold is reached and returns LOW when the overload condition is cleared. The OLF1, OLF2, BCF1, and BCF2 bits will be LOW at the end of initial power-on soft-start. In the static mode the output current through the linears is limited to 990mA typ. When a 19.3V line is connected onto a VOUT1 or VOUT2 pin that has been set to 13.3V, the linear will then enter a dynamic back current limit state. When a dynamic back current limit of greater that 125mA typ is sensed at the lower FET of the linear for a period greater that 100µs, the output is disabled for a period of 5ms and the BCF1 and BCF2 bits are set. If the 19.3V remains connected, the output will cycle through the ON = 100µs/OFF = 5ms. The output will recover when the fault is removed. Thermal Protection This IC is protected against overheating. When the junction temperature exceeds +150°C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW when the junction is cooled down to +130°C (typical). The FLT pin serves as an interrupt for the processor when an over temperature, overcurrent or backwards overcurrent fault is detected by the LNB controller or when both channels are disabled by the I2C EN1 and EN2 bits being set low. Should the I2C lose power (for example by shorting BYP pin to ground), it is designed to power up with all control bits set to 0 (particularly the EN1 and EN2 bits). This prevents the device from coming back up in a state not desired by the host controller. If the host controller sees a FLT low, it should read the I2C bits and find both EN1 and EN2 bits low. When it desires one or both to be high, it should re-write the I2C to the desired state. External Output Voltage Selection The output voltage can be selected by the I2C bus. Additionally, the package offers two pins (SELVTOP1 and SELVTOP2) for independent 13 through 19V output voltage selection. I2C Bus Interface for ISL6422 (Refer to Phillips I2C Specification, Rev. 2.1) Data transmission from the main microprocessor to the ISL6422 and vice versa takes place through the two-wire I2C bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines. They are connected to a positive supply voltage via a pull-up resistor. (Pull-up resistors to positive supply voltage must be externally connected.) When the bus is free, both lines are HIGH. The output stages of ISL6422 will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100Kbps in the standard mode or up to 400Kbps in the fast mode. The level of logic “0” and logic “1” depends on the value of VDD as per the Electrical Specification table on page 5. One clock pulse is generated for each data bit transferred. TABLE 1. VSPEN1, VSPEN2 VTOP1, VTOP2 VBOT1, VBOT2 SELVTOP1, SELVTOP2 VOUT1, VOUT12 0 X 0 0 13.3V 0 X 1 0 14.3V 0 0 X 1 18.3V 0 1 X 1 19.3V 1 0 0 X 13.3V 1 0 1 X 14.3V 1 1 0 X 18.3V 1 1 1 X 19.3V ISL6422 |
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