6

FN9181.2

April 4, 2006

Minimum Duty Cycle

VERR < 0.6V

-

-

0

%

Maximum Duty Cycle (per half-cycle)

-

94

-

%

RTD = 2.00k

Ω, CT = 220pF

-

97

-

%

RTD = 2.00k

Ω, CT = 470pF

-

99

-

%

Zero Duty Cycle VERR Voltage

0.85

-

1.20

V

VERR to PWM Comparator Input Offset

0.7

0.8

0.9

V

VERR to PWM Comparator Input Gain

0.31

0.33

0.35

V/V

Common Mode (CM) Input Range

(Note 4)

0

-

4.45

V

OSCILLATOR

Frequency Accuracy, Overall

(Note 4)

165

183

201

kHz

-10

-

10

%

Frequency Variation with VDD

-0.3

1.7

%

Temperature Stability

-4.5

-

%

-

1.5

-

%

Charge Current

-193

-200

-207

µA

Discharge Current Gain

19

20

23

µA/µA

CT Valley Voltage

Static Threshold

0.75

0.80

0.88

V

CT Peak Voltage

Static Threshold

2.75

2.80

2.88

V

CT Pk-Pk Voltage

Static Value

1.92

2.00

2.05

V

RTD Voltage

1.97

2.00

2.03

V

RESDEL Voltage Range

0

-

2.00

V

1.95

2.0

2.05

V/V

CTBUF Offset from GND

0.34

0.40

0.44

V

CTBUF VOH

-

-

0.10

V

CTBUF VOL

-

-

0.10

V

OUTPUT

High Level Output Voltage (VOH)

-

0.5

1.0

V

Low Level Output Voltage (VOL)

-

0.5

1.0

V

Rise Time

-

110

200

ns

Fall Time

-

90

150

ns

UVLO Output Voltage Clamp

-

-

1.25

V

Output Delay/Advance Range

OUTLLN/OUTLRN relative to OUTLL/OUTLR

-

-

3

ns

-40

-

-300

ns

40

-

300

ns

Delay/Advance Control Voltage Range

OUTLLN/OUTLRN relative to OUTLL/OUTLR

OUTLxN Delayed

2.575

-

5.000

V

OUTLxN Advanced

0

-

2.425

V

Electrical Specifications

Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application

schematic. 9V < VDD < 20V, RTD = 10.0k

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ISL6752