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ISL6549CR Datasheet(PDF) 14 Page - Intersil Corporation |
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ISL6549CR Datasheet(HTML) 14 Page - Intersil Corporation |
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14 / 18 page  14 FN9168.2 September 22, 2006 FET is particularly slow in these parameters, there is a greater chance that shoot-through current will occur. As referenced in the “Block Diagram” on page 2, the UGATE signal is referenced to PHASE signal. The deadtime comparator also looks at the difference (UGATE - PHASE). This is significant when viewing the gate driver waveforms on an oscilloscope. One simple indication of shoot-through (or insufficient deadtime) is when the UGATE and LGATE signals overlap. But in this case, one should look at UGATE-PHASE (either by a math function of the two signals, or by using a differential probe measurement) compared to LGATE. Figure 12 shows an example of this. It looks as if the UGATE and LGATE signals have crossed, but the UGATE-PHASE signal does not cross the LGATE. One important consideration is negative spikes on the PHASE node as it goes low. The upper FET is turning off, but before the lower FET can take over, stray inductance in the layout (on the board, or even the inductance of some components, such as D2PAK FETs) can contribute to the PHASE going negative. There is no maximum spec for PHASE spike below GND, however, there is an absolute maximum rating for (BOOT - PHASE) of 7V; exceeding this limit can cause damage to the IC, and possibly to the system. Since the BOOT signal is typically 5V above the PHASE node most of the time, it only takes a few volts of a spike on either signal to exceed the limit. A good design should be characterized by using the math function or differential probe, and monitoring these signals for compliance, especially during full loads, where the signals are usually the noisiest. Slowing down the turn-off of the upper FET may help, while at other times, sometimes the problem may just be the choice of FETs. If the power efficiency of the system is important, then other FET parameters are also considered. Efficiency is a measure of power losses from input to output, and it contains two major components: losses in the IC (mostly in the gate drivers) and losses in the FETs. Optimizing the sum involves many trade-offs (for example, raising the voltage of the gate drivers typically adds power to the IC side, but may reduce some power on the FET side). For low duty cycle applications (such as 12V in to 1.5V out), the upper FET is usually chosen for low gate charge, since switching losses are key, while the lower FET is chosen for low RDS(ON), since it is on most of the time. For high duty cycles (such as 3.3V in to 2.5V out), the opposite is true. In summary, the following parameters may need to be considered in choosing the right FETs for an application: drain-source breakdown voltage rating, gate-source rating, maximum current, thermal and package considerations, low gate threshold voltage, gate charge, RDS(ON) at 4.5V, and switching speed. And, of course, the board layout constraints and cost also are factored into the decision. Linear FET Considerations The linear FET is chosen primarily for thermal performance. The current for the linear output is generally limited by the power dissipation (P = (VIN2 - VOUT2) * I), and the FET thermal rating for getting the heat out of the package, and spreading it out on the board, especially when no heatsinks or airflow is available. It is generally not recommended to parallel two FETs in order to get higher current or to spread out the heat, as the FETs would need to be very well-matched in order to share the current properly. Should this approach be desired, and as perfectly matched FETs are seldom available, a small resistor, or PCB trace of suitable resistance placed in the source of each of the FETs can be used to improve the current balance. The maximum VOUT2 voltage allowed is determined by several factors: • Power dissipation, as described earlier • Input voltage available • LDO_DR voltage • FET chosen The voltage cannot be any higher than the input voltage available, and the max VIN2 is 12V (13.2V for a ±10% supply). The LDO_DR voltage is driven from the VCC12 rail; allowing for headroom, the typical maximum voltage is 11V (lower as VCC12 goes to its minimum of 10.8V). So the maximum output voltage will be at least a VGS drop (which includes the FET threshold voltage) below the 11V, at the maximum load current; some additional headroom is usually needed to handle transient conditions. So a practical typical value around 8V may be possible, but remember to also factor in the variations for worst case conditions on VIN2 and the FET parameters. As long as the VIN2 is low enough such that headroom versus VCC12 is not a problem, then the maximum output voltage is just below VIN2, based on the RDS(ON) drop at maximum current. The input supply for VIN2 can also be any available supply less than 12V, subject to the considerations above. The drain-source breakdown voltage of the FET should be greater FIGURE 12. GATE DRIVER WAVEFORMS UGATE (4V/DIV) UGATE-PHASE (4V/DIV) PHASE (4V/DIV) LGATE (4V/DIV) GND> GND> GND> GND> ISL6549 |
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