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FMS6419 Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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FMS6419 Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 10 page REV. 5C April 2005 7 FMS6419 DATA SHEET 1 2 3 4 INMUX RINA RINB GINA FSEL VSSRGB VCCA VSS 28 27 26 25 5 6 7 GINB BINA BINB ROUT GOUT BOUT 24 23 22 8 CVMUX YOUT 21 9 10 NC NC VCCO COUT 20 19 11 12 13 VSSA AUXIN CIN CVOUT NC VSSYC 18 17 16 14 YIN NC 15 FMS6419MS28 28-pin SSOP Applications DC Levels At any given time, the input signal’s DC levels must be between 0.0V and 1.3V to utilize the optimal headroom and to avoid clipping on the outputs. The Y channel should nominally have the Sync Tip at ground and be a 1V signal. The C channel should ride around the 0.5V level. This will ensure that the filter will utilize the optimal headroom and avoid clipping. DC Coupled Output Applications The 220 µF capacitor coupled with the 150Ω termination forms a high pass filter that blocks the DC while passing the video frequencies and avoiding tilt. Lower values such as Pin Configuration 10 µF would create a problem. By AC coupling, the average DC level is zero. Thus, the output voltages of all channels will be centered around zero. Alternately, DC coupling the output of the FMS6419 is allowable, but not recommended. There are several tradeoffs: The average DC level on the out- puts will be 2V. Each output will dissipate an additional 40mW nominally. The application will need to accommodate a 1V DC offset sync tip. Also, it is recommended to limit one 150 Ω load per output. Driving the Digital Pins with 3.3V or 5V Logic Either is allowed as long as the V ih and Vil are adhered to. Note: Pin Assignments table follows on page 8. |
Similar Part No. - FMS6419_05 |
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Similar Description - FMS6419_05 |
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