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ISL6597 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6597 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 10 page  7 FN9165.0 November 22, 2006 PWM line of ISL6597 (assuming an Intersil PWM controller is used). Bootstrap Considerations This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size: where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The ΔVBOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two HAT2168 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 12nC at 5V (VGS) gate-source voltage. Then the QGATE is calculated to be 26.4nC at 5.5V PVCC level. We will assume a 100mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.264 μF is required. The next larger standard value capacitance is 0.33µF. A good quality ceramic capacitor is recommended. Power Dissipation Package power dissipation is mainly a function of the switching frequency (FSW), the output drive impedance, the external gate resistance, and the selected MOSFET’s internal gate resistance and total gate charge. Calculating the power dissipation in the driver for a desired application is critical to ensure safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of +125°C. The maximum allowable IC power dissipation for the 16 lead 4x4 QFN packages, with an exposed heat escape pad, is around 2W. See Layout Considerations paragraph for thermal transfer improvement suggestions. When designing the driver into an application, it is recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses due to the gate charge of MOSFETs and the driver’s internal circuitry and their corresponding average driver current can be estimated with Equations 2 and 3, respectively, where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver’s total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. The factor 2 is the number of active channels. The IQ VCC product is the quiescent power of the driver without capacitive load and is typically negligible. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2, should be a short to avoid interfering with the operation shoot-through protection circuitry) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as: C BOOT_CAP Q GATE ΔV BOOT_CAP -------------------------------------- ≥ Q GATE Q G1 PVCC • V GS1 ------------------------------------ N Q1 • = (EQ. 1) 50nC 20nC FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE ΔV BOOT (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 QGATE = 100nC 1.8 2.0 P Qg_TOT 2P Qg_Q1 P Qg_Q2 + () • I Q VCC • + = (EQ. 2) P Qg_Q1 Q G1 PVCC2 • V GS1 --------------------------------------- F SW • N Q1 • = P Qg_Q2 Q G2 PVCC2 • V GS2 --------------------------------------- F SW • N Q2 • = I DR 2 Q G1 N Q1 • V GS1 ------------------------------ Q G2 N Q2 • V GS2 ------------------------------ + ⎝⎠ ⎜⎟ ⎛⎞ • F SW I Q + • = (EQ. 3) P DR 2P DR_UP P DR_LOW + () • I Q VCC • + = (EQ. 4) P DR_UP R HI1 R HI1 R EXT1 + -------------------------------------- R LO1 R LO1 R EXT1 + ---------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ P Qg_Q1 2 --------------------- • = P DR_LOW R HI2 R HI2 R EXT2 + -------------------------------------- R LO2 R LO2 R EXT2 + ---------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ P Qg_Q2 2 --------------------- • = R EXT2 R G1 R GI1 N Q1 ------------- + = R EXT2 R G2 R GI2 N Q2 ------------- + = ISL6597 |
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