6

FN9157.3

July 31, 2006

Description

Operation

Designed for versatility and speed, the ISL6594A and

ISL6594B MOSFET drivers control both high-side and low-

side N-Channel FETs of a half-bridge power train from one

externally provided PWM signal.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial

startup; the upper gate (UGATE) is held low and the lower

gate (LGATE), controlled by the Pre-POR overvoltage

protection circuits, is connected to the PHASE. Once the

VCC voltage surpasses the VCC Rising Threshold (See

Electrical Specifications), the PWM signal takes control of

gate transitions. A rising edge on PWM initiates the turn-off

of the lower MOSFET (see Timing Diagram). After a short

Specifications section. Adaptive shoot-through circuitry

monitors the LGATE voltage and determines the upper gate

MOSFETs from conducting simultaneously. Once this delay

and the upper MOSFET turns on.

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See next section for

MOSFET.

Adaptive Zero Shoot-Through Deadtime Control

These drivers incorporate an adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other

has turned off.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it drops below 1.75V, at which time the

UGATE is released to rise after 20ns of propagation delay.

Once the PHASE is high, the adaptive shoot-through

circuitry monitors the PHASE and UGATE voltages during a

PWM falling edge and the subsequent UGATE turn-off. If

either the UGATE falls to less than 1.75V above the PHASE

or the PHASE falls to less than +0.8V, the LGATE is

released to turn on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

PWM

UGATE

LGATE

1.18V<PWM<2.36V

0.76V<PWM<1.96V

FIGURE 1. TIMING DIAGRAM

ISL6594A, ISL6594B