8

FN9157.3

July 31, 2006

driver current can be estimated with Equations 2 and 3,

respectively,

respectively; UVCC and LVCC are the drive voltages for

product is the quiescent power of the driver without

capacitive load and is typically 116mW at 300kHz.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

typical upper and lower gate drives turn-on transition path.

The power dissipation on the driver can be roughly

estimated as:

Layout Considerations

For heat spreading, place copper underneath the IC whether

it has an exposed pad or not. The copper area can be

extended beyond the bottom area of the IC and/or

connected to buried copper plane(s) with thermal vias. This

combination of vias for vertical heat escape, extended

copper plane, and buried planes for heat spreading allows

the IC to achieve its full thermal potential.

Place each channel power component as close to each

other as possible to reduce PCB copper losses and PCB

parasitics: shortest distance between DRAINs of upper FETs

and SOURCEs of lower FETs; shortest distance between

DRAINs of lower FETs and the power ground. Thus, smaller

amplitudes of positive and negative ringing are on the

switching edges of the PHASE node. However, some space

in between the power components is required for good

airflow. The traces from the drivers to the FETs should be

kept short and wide to reduce the inductance of the traces

and to promote clean drive signals.

P

Qg_TOT

P

Qg_Q1

P

Qg_Q2

I

Q

VCC

•

++

=

(EQ. 2)

P

Qg_Q1

Q

G1

•

V

GS1

---------------------------------------

F

SW

•

N

Q1

•

=

P

Qg_Q2

Q

G2

•

V

GS2

--------------------------------------

F

SW

•

N

Q2

•

=

I

DR

Q

G1

UVCC

N

Q1

•

•

V

GS1

------------------------------------------------------

Q

G2

LVCC

N

Q2

•

•

V

GS2

-----------------------------------------------------

+

⎝⎠

⎜⎟

⎛⎞

F

SW

I

Q

+

•

=

(EQ. 3)

P

DR

P

DR_UP

P

DR_LOW

I

Q

VCC

•

++

=

(EQ. 4)

P

DR_UP

R

HI1

R

HI1

R

EXT1

+

--------------------------------------

R

LO1

R

LO1

R

EXT1

+

----------------------------------------

+

⎝⎠

⎜⎟

2

---------------------

•

=

P

DR_LOW

R

HI2

R

HI2

R

EXT2

+

--------------------------------------

R

LO2

R

LO2

R

EXT2

+

----------------------------------------

+

⎝⎠

⎜⎟

2

---------------------

•

=

R

EXT1

R

G1

R

GI1

N

Q1

-------------

+

=

R

EXT2

R

G2

R

GI2

N

Q2

-------------

+

=

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Q1

D

S

G

BOOT

PHASE

UVCC

LVCC

Q2

D

S

G

ISL6594A, ISL6594B