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X40434V14IZ-B Datasheet(PDF) 9 Page - Intersil Corporation

Part # X40434V14IZ-B
Description  Triple Voltage Monitor with Integrated CPU Supervisor
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X40434V14IZ-B Datasheet(HTML) 9 Page - Intersil Corporation

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9
FN8251.1
May 24, 2006
Setting a VTRIPx Voltage (x = 1, 2, 3)
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage
to be stored is higher or lower than the present value.
For example, if the present VTRIPx is 2.9 V and the
new VTRIPx is 3.2 V, the new voltage can be stored
directly into the VTRIPx cell. If however, the new setting
is to be lower than the present setting, then it is neces-
sary to “reset” the VTRIPx voltage before setting the
new value.
Setting a Higher VTRIPx Voltage (x = 1, 2, 3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin Vcc(V1MON), V2MON or V3MON.
Then, a programming voltage (Vp) must be applied to the
WDO pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h, fol-
lowed by the Byte Address 01h for VTRIP1, 09h for
VTRIP2, and 0Dh for VTRIP3, and a 00h Data Byte in order
to program VTRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation. To
check if the VTRIPX has been set, set VXMON to a value
slightly greater than VTRIPX (that was previously set).
Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE, V2FAIL and V3FAIL)
switch. The voltage at which this occurs is the VTRIPX
(actual).
CASE A
Now if the desired VTRIPX is greater than the VTRIPX
(actual), then add the difference between VTRIPX
(desired) – VTRIPX (actual) to the original VTRIPX
desired. This is your new VTRIPX that should be
applied to VXMON and the whole sequence should be
repeated again (see Figure 5).
CASE B
Now if the VTRIPX (actual), is higher than the VTRIPX
(desired), perform the reset sequence as described in
the next section. The new VTRIPX voltage to be applied
to VXMON will now be: VTRIPX (desired) – (VTRIPX
(actual) – VTRIPX (desired)).
Note: This operation does not corrupt the memory array.
Setting a Lower VTRIPx Voltage (x = 1, 2, 3)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed
by 00h for the Data Byte in order to reset VTRIPx. The
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of VTRIPx becomes a nomi-
nal value of 1.7V or lesser.
Notes: 1. This operation does not corrupt the memory array.
2. Set VCC ≅ 1.5(V2MON or V3MON), when setting
VTRIP2 or VTRIP3 respectively.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 11.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430,
X40431, X40434, X40435 will not acknowledge any
data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
7
6
543
21
0
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
X40430, X40431, X40434, X40435


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